diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index b0beb5b..6b1e7a9 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -414,11 +414,31 @@ trait ShinTopWatchDog{ this: ShinTopBase =>
       wdtSMCnt(i) := 0.U
     }
 
-    assert( wdtSMCnt(i) <= interface.io.cReg.wdtTarCnt(i+1), "Assert Failed! wdtSMCnt is larger than wdtTarCnt, Special situation?" )
+    assert( wdtSMCnt(i) <= interface.io.cReg.wdtTarCnt(i+1), s"Assert Failed! wdtSMCnt($i) is larger than wdtTarCnt, Special situation?" )
     
     interface.io.wdtTrigger(i+1) := wdtSMCnt(i) === interface.io.cReg.wdtTarCnt(i+1)
   }
-  interface.io.wdtTrigger(0) := slaveParser.io.isRecWdtTrigger
+
+
+  val isWdtRecEnable = RegInit(false.B)
+  val wdtRecCnt = Reg(UInt(32.W))
+
+  when( upCDRIn.io.axis.fire & upCDRIn.io.axis.bits.tlast ){
+    isWdtRecEnable := false.B
+  } .elsewhen( ~isWdtRecEnable & downCDROut.io.axis.fire & interface.io.cReg.wdtEnable.extract(0) ){
+    isWdtRecEnable := true.B
+  }
+
+  when( isWdtRecEnable & (wdtRecCnt < interface.io.cReg.wdtTarCnt(0)) ){
+    wdtRecCnt := wdtRecCnt + 1.U
+  } .elsewhen( ~isWdtRecEnable ){
+    wdtRecCnt := 0.U
+  }
+
+  assert( wdtRecCnt < interface.io.cReg.wdtTarCnt(0), "Assert Failed! wdtRecCnt is larger than wdtTarCnt, Special situation?" )
+
+  interface.io.wdtTrigger(0) := wdtRecCnt === interface.io.cReg.wdtTarCnt(0)
+
 
 
 }
diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala
index ba6f4df..9980f0a 100644
--- a/src/main/scala/backBoard/shin/SlaveParser.scala
+++ b/src/main/scala/backBoard/shin/SlaveParser.scala
@@ -70,8 +70,6 @@ class SlaveParserIO extends Bundle{
 
   val intHWTrig   = Output(Vec(2, Bool()))
   val intHWClr    = Input (Vec(2, Bool()))
-
-  val isRecWdtTrigger = Output(Bool())
 }
 
 abstract class SlaveParserBase extends Module{
@@ -707,9 +705,8 @@ trait SlaveParserProbe{ this: SlaveParserBase =>
 
 
   // val ProbeRecAim  = 511.U
-  val probeRecCnt = RegInit(0.U(32.W))
-  val isWatchDogOverflow = probeRecCnt === io.cReg.wdtTarCnt(0)
-  io.isRecWdtTrigger := isWatchDogOverflow
+  val probeRecCnt = RegInit(0.U(9.W))
+  val isWatchDogOverflow = probeRecCnt.andR