diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index 41c20dd..e43ce2d 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -16,8 +16,9 @@ class CommonRegisterBundle extends Bundle{
   val encryptKey   = UInt(128.W)
   val isEncrypt    = Bool()
 
-  val intEnable = UInt(16.W)
-  val intStatus = UInt(16.W)
+  val intEnable = UInt(32.W)
+  val intStatus = UInt(32.W)
+  val intMode   = UInt(16.W)
 
 
   // val upRecErrorCnt   = UInt(32.W)
@@ -257,8 +258,18 @@ abstract class InterfaceBase extends Module{
         (addr === "h60".U ) -> cReg.isEncrypt,
         (addr === "h70".U ) -> cReg.intEnable(7,0),
         (addr === "h71".U ) -> cReg.intEnable(15,8),
-        (addr === "h72".U ) -> cReg.intStatus(7,0),
-        (addr === "h73".U ) -> cReg.intStatus(15,8),
+        (addr === "h72".U ) -> cReg.intEnable(23,16),
+        (addr === "h73".U ) -> cReg.intEnable(31,24),
+
+        (addr === "h74".U ) -> cReg.intStatus(7,0),
+        (addr === "h75".U ) -> cReg.intStatus(15,8),
+        (addr === "h76".U ) -> cReg.intStatus(23,16),
+        (addr === "h77".U ) -> cReg.intStatus(31,24),
+
+        (addr === "h7c".U ) -> cReg.intMode(7,0),
+        (addr === "h7d".U ) -> cReg.intMode(15,8),
+
+
         (addr === "hc0".U ) -> Cat( sReg.isDevOnRightModify, sReg.isDevOnRight, 0.U(3.W) ),
         (addr === "hc2".U ) -> sReg.indexOfRightDev(7,0),
         (addr === "hc3".U ) -> sReg.indexOfRightDev(13,8),
@@ -738,14 +749,27 @@ trait InterfaceSystem{ this: InterfaceBase =>
 
   cReg.intEnable :=
     Cat(
+      1.U(1.W), //复位中断，时钟为1
+      RegEnable( dataw(6,0), 0.U, isEnW & addrw === "h73".U ),
+      RegEnable( dataw, 0.U, isEnW & addrw === "h72".U ),
       RegEnable( dataw, 0.U, isEnW & addrw === "h71".U ),
-      RegEnable( dataw, 0.U, isEnW & addrw === "h70".U )
+      RegEnable( dataw, 0.U, isEnW & addrw === "h70".U ),
     )
 
-  val intStatus = for( _ <- 0 until 16 ) yield { RegInit(false.B) }
+  val intStatus = for( i <- 0 until 32 ) yield {
+    if( i != 31 ) {RegInit(false.B)} else { RegInit(true.B) }
+  }
   cReg.intStatus := Cat( intStatus.reverse )
 
+  cReg.intMode :=
+    Cat(
+      RegEnable( dataw, 0.U, isEnW & addrw === "h7d".U ),
+      RegEnable( dataw, 0.U, isEnW & addrw === "h7c".U ),
+    )
 
+  val isLevelInt = cReg.intMode.extract(15) === false.B
+  val isPulseInt = cReg.intMode.extract(15) === true.B
+  val intPulseWidth = cReg.intMode(14,0)
 
   //主站发送完成
   when( io.intMstTrig(0) & cReg.intEnable(0) ){
@@ -762,15 +786,8 @@ trait InterfaceSystem{ this: InterfaceBase =>
 
   //主站接收看门狗溢出
 
-  //下行接收硬件错误
-  when( io.intHWTrig(0) ){
-    intStatus(5) := true.B
-  }
 
-  when( io.intHWTrig(1) ){
-    intStatus(6) := true.B
-  }
-  //上行接收硬件错误
+
 
 
   //从站SM请求
@@ -780,21 +797,60 @@ trait InterfaceSystem{ this: InterfaceBase =>
     }
   }
 
+  //下行接收硬件错误
+  when( io.intHWTrig(0) ){
+    intStatus(29) := true.B
+  }
+
+  when( io.intHWTrig(1) ){
+    intStatus(30) := true.B
+  }
+  //上行接收硬件错误
 
   //写清中断
   for( i <- 0 until 8 ){
-    when( dataw.extract(i) & isEnW & addrw === "h74".U ){
-      intStatus(i) := false.B
+    when( dataw.extract(i) & isEnW & addrw === "h78".U ){
+      intStatus(i)    := false.B
     }
-    when( dataw.extract(i) & isEnW & addrw === "h75".U ){
-      intStatus(i+8) := false.B
+    when( dataw.extract(i) & isEnW & addrw === "h79".U ){
+      intStatus(i+8)  := false.B
+    }
+    when( dataw.extract(i) & isEnW & addrw === "h7a".U ){
+      intStatus(i+16) := false.B
+    }
+    when( dataw.extract(i) & isEnW & addrw === "h7b".U ){
+      intStatus(i+24) := false.B
     }
   }
 
-  io.intHWClr(0) := dataw.extract(5) & isEnW & addrw === "h74".U 
-  io.intHWClr(1) := dataw.extract(6) & isEnW & addrw === "h74".U 
+  io.intHWClr(0) := dataw.extract(5) & isEnW & addrw === "h7b".U 
+  io.intHWClr(1) := dataw.extract(6) & isEnW & addrw === "h7b".U 
 
-  io.interrupt := intStatus.reduce(_|_)
+  val intPulse = RegInit(false.B)
+  val intPulseResetCnt = RegInit(0.U(15.W))
+  
+  val trigIntPulse = 
+    (io.intMstTrig(0) & cReg.intEnable(0)) | //主站发送完成
+    (io.intMstTrig(1) & cReg.intEnable(1)) | //主站接收完成
+    false.B | //主站发送周期到了
+    false.B | //主站接收看门狗溢出
+    (0 until 8).map{ i => io.intSlvTrig(i) & cReg.intEnable(8+i)}.reduce(_|_) | //从站SM请求
+    io.intHWTrig(0) | io.intHWTrig(1)//下行接收硬件错误
+
+  when( intPulseResetCnt === intPulseWidth ){
+    intPulse := false.B
+  } .elsewhen( trigIntPulse ){
+    intPulse := true.B
+  }
+
+  when( trigIntPulse ){
+    intPulseResetCnt := 0.U
+  } .elsewhen( (intPulseResetCnt < intPulseWidth) & (intPulse === true.B) ){
+    intPulseResetCnt := intPulseResetCnt + 1.U
+  }
+
+  io.interrupt := Mux( isLevelInt, intStatus.reduce(_|_), intPulse)
+  
 
 }