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@@ -5,7 +5,6 @@ import chisel3.util._
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class ShinTopIO extends Bundle{
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val clk8x = Input(Bool())
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val dDatIn = Input(Bool())
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val dDatOut = Output(Bool())
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@@ -56,18 +55,50 @@ class ShinTopIO extends Bundle{
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abstract class ShinTopBase extends Module{
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def isMultiCLK: Int = 8
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val io: ShinTopIO = IO(new ShinTopIO)
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// val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) }
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// val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) }
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val slaveParser = Module(new SlaveParser )
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val masterParser = Module(new MasterParser)
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val downCDRIn = Module(new CDRIn)
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val upCDRIn = Module(new CDRIn)
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val ( downCDRIn, upCDRIn ) =
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if( isMultiCLK == 0 ){
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val clk8x = IO(Input(Bool()))
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val down = Module(new CDRIn with CDRInOverSample )
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val up = Module(new CDRIn with CDRInOverSample )
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down.overCLK := clk8x
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up.overCLK := clk8x
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(down, up)
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} else{
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val multiCLK = IO(Input(Vec(isMultiCLK, Bool())))
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val down = Module(new CDRIn with CDRInMultiSample)
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val up = Module(new CDRIn with CDRInMultiSample)
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down.multiCLK := multiCLK
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up.multiCLK := multiCLK
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(down, up)
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}
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// val downCDRIn = if( isMultiCLK == 0 ) { Module(new CDRIn with CDRInOverSample ) } else { Module(new CDRIn with CDRInMultiSample) }
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// val upCDRIn = if( isMultiCLK == 0 ) { Module(new CDRIn with CDRInOverSample ) } else { Module(new CDRIn with CDRInMultiSample) }
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// if( isMultiCLK == 0 ){
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// val clk8x = IO(Input(Bool()))
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// downCDRIn.overCLK := clk8x
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// upCDRIn.overCLK := clk8x
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// } else {
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// val multiCLK = IO(Input(Vec(isMultiCLK, Bool())))
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// downCDRIn.multiCLK := multiCLK
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// upCDRIn.multiCLK := multiCLK
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// }
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val downCDROut = Module(new CDROut)
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val upCDROut = Module(new CDROut)
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@@ -79,11 +110,9 @@ abstract class ShinTopBase extends Module{
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io.interrupt := interface.io.interrupt
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downCDRIn.io.serDat := io.dDatIn
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downCDRIn.io.overCLK := io.clk8x
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downCDRIn.io.initEncryptor := interface.io.initEncryptor
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upCDRIn.io.serDat := io.uDatIn
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upCDRIn.io.overCLK := io.clk8x
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upCDRIn.io.initEncryptor := interface.io.initEncryptor
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io.dDatOut := downCDROut.io.serDat
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