编译通过

This commit is contained in:
Ruige Lee
2025-07-22 09:35:06 +08:00
parent bf8fce2671
commit 7c632c8c1b
4 changed files with 73 additions and 26 deletions

View File

@@ -5,7 +5,6 @@ import chisel3.util._
class ShinTopIO extends Bundle{
val clk8x = Input(Bool())
val dDatIn = Input(Bool())
val dDatOut = Output(Bool())
@@ -56,18 +55,50 @@ class ShinTopIO extends Bundle{
abstract class ShinTopBase extends Module{
def isMultiCLK: Int = 8
val io: ShinTopIO = IO(new ShinTopIO)
// val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) }
// val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) }
val slaveParser = Module(new SlaveParser )
val masterParser = Module(new MasterParser)
val downCDRIn = Module(new CDRIn)
val upCDRIn = Module(new CDRIn)
val ( downCDRIn, upCDRIn ) =
if( isMultiCLK == 0 ){
val clk8x = IO(Input(Bool()))
val down = Module(new CDRIn with CDRInOverSample )
val up = Module(new CDRIn with CDRInOverSample )
down.overCLK := clk8x
up.overCLK := clk8x
(down, up)
} else{
val multiCLK = IO(Input(Vec(isMultiCLK, Bool())))
val down = Module(new CDRIn with CDRInMultiSample)
val up = Module(new CDRIn with CDRInMultiSample)
down.multiCLK := multiCLK
up.multiCLK := multiCLK
(down, up)
}
// val downCDRIn = if( isMultiCLK == 0 ) { Module(new CDRIn with CDRInOverSample ) } else { Module(new CDRIn with CDRInMultiSample) }
// val upCDRIn = if( isMultiCLK == 0 ) { Module(new CDRIn with CDRInOverSample ) } else { Module(new CDRIn with CDRInMultiSample) }
// if( isMultiCLK == 0 ){
// val clk8x = IO(Input(Bool()))
// downCDRIn.overCLK := clk8x
// upCDRIn.overCLK := clk8x
// } else {
// val multiCLK = IO(Input(Vec(isMultiCLK, Bool())))
// downCDRIn.multiCLK := multiCLK
// upCDRIn.multiCLK := multiCLK
// }
val downCDROut = Module(new CDROut)
val upCDROut = Module(new CDROut)
@@ -79,11 +110,9 @@ abstract class ShinTopBase extends Module{
io.interrupt := interface.io.interrupt
downCDRIn.io.serDat := io.dDatIn
downCDRIn.io.overCLK := io.clk8x
downCDRIn.io.initEncryptor := interface.io.initEncryptor
upCDRIn.io.serDat := io.uDatIn
upCDRIn.io.overCLK := io.clk8x
upCDRIn.io.initEncryptor := interface.io.initEncryptor
io.dDatOut := downCDROut.io.serDat