编译通过

2025-07-22 09:35:06 +08:00
parent bf8fce2671
commit 7c632c8c1b
4 changed files with 73 additions and 26 deletions
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -8,14 +8,13 @@ import chisel3.util._
 class CDRInIO extends Bundle{
  val axis = Decoupled(new AXIS_Bundle(8))
  val serDat = Input(Bool())
-  val overCLK = Input(Bool())

  val initEncryptor = Flipped(Valid(UInt(128.W)))
 }


 abstract class CDRInBase extends Module{
-  def sampleRate: Int = 4
+

  val io: CDRInIO = IO(new CDRInIO)

@@ -23,19 +22,24 @@ abstract class CDRInBase extends Module{
  encryptor.io.init := io.initEncryptor
  encryptor.io.op.ready := io.axis.fire

+  val syncSerDat = Wire(Bool())
 }

 trait CDRInOverSample{ this: CDRInBase =>
-  val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) }
+  val overCLK = IO(Input(Bool()))
+  val sampleRate: Int = 4
+  require(sampleRate >= 4)

-  val arbCnt  = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) }
+  val sampleReg = withClockAndReset(overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) }
+
+  val arbCnt  = withClockAndReset(overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) }
  arbCnt := Cat( arbCnt(sampleRate-2,0), arbCnt.extract(sampleRate-1) )
-  val arbLock = withClockAndReset(io.overCLK.asClock, reset.asBool){ Reg(UInt( sampleRate.W )) }
+  val arbLock = withClockAndReset(overCLK.asClock, reset.asBool){ Reg(UInt( sampleRate.W )) }
  when( sampleReg(0) ^ sampleReg(1) ){
    arbLock := arbCnt
  }

-  val asyncSerDat = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegNext(
+  val asyncSerDat = withClockAndReset(overCLK.asClock, reset.asBool){ RegNext(
    Mux1H(
      (for { i <- 0 until sampleRate; j <- 0 until sampleRate } yield {
        //跳变沿到来锁定的位置        锁定拍当前所在的位置          选择锁定拍后一拍的值认为是正确值
@@ -45,21 +49,27 @@ trait CDRInOverSample{ this: CDRInBase =>
  )}


-  val syncSerDat = ShiftRegister( asyncSerDat, 2 )
+  syncSerDat := ShiftRegister( asyncSerDat, 2 )

 }

 trait CDRInMultiSample{ this: CDRInBase =>
-  val clkNum: Int = 16
+  
+  val clkNum: Int = 8
+  require(clkNum >= 4)
+
+  //multiCLK 需要按照超前相位接线，即0为最后到达，1次后
+  val multiCLK = IO(Input(Vec(clkNum, Bool())))
+
  // val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) }
  val sampleReg = for( i <- 0 until clkNum ) yield {
-    withClockAndReset(io.multiCLK(i).asClock, reset.asBool){ ShiftRegisters( io.serDat, 2 ) }
+    withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
  }

  // val arbCnt  = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) }
  // arbCnt := Cat( arbCnt(sampleRate-2,0), arbCnt.extract(sampleRate-1) )
  val arbCnt = RegInit("b1".U(clkNum.W))
-  arbCnt := Cat( arbCnt(sampleRate-2,0), arbCnt.extract(clkNum-1) )
+  arbCnt := Cat( arbCnt(clkNum-2,0), arbCnt.extract(clkNum-1) )

  // val arbLock = withClockAndReset(io.overCLK.asClock, reset.asBool){ Reg(UInt( sampleRate.W )) }
  // when( sampleReg(0) ^ sampleReg(1) ){
@@ -91,7 +101,7 @@ trait CDRInMultiSample{ this: CDRInBase =>


  // val syncSerDat = ShiftRegister( asyncSerDat, 2 )
-  val syncSerDat = ShiftRegister( asyncSerDat, 2 )
+  syncSerDat := ShiftRegister( asyncSerDat, 2 )

 }

@@ -114,7 +124,6 @@ trait CDRInAxis{ this: CDRInBase =>
  val bitCnt = Reg(UInt(4.W))
  val byteCnt = RegInit(0.U((12+1).W))

-  val syncSerDat: Bool
  val checkSFD = RegInit( 0.U(20.W) ); checkSFD := Cat( checkSFD(18,0), syncSerDat )

  val shiftData = Dualb4b5Decoder(checkSFD(9,0))
@@ -183,5 +192,6 @@ trait CDRInAxis{ this: CDRInBase =>
 }


-class CDRIn extends CDRInBase with CDRInOverSample with CDRInAxis
+class CDRIn extends CDRInBase 
+with CDRInAxis

--- a/src/main/scala/backBoard/ebus/RoCC2CDR.scala
+++ b/src/main/scala/backBoard/ebus/RoCC2CDR.scala
@@ -53,13 +53,18 @@ abstract class RoCC2CDRImplBase(outer: RoCC2CDR)(implicit p: Parameters) extends
  val cdrInio  = IO(Input(new RocCC2CDRInIO))
  val cdrOutio = IO(Output(new RocCC2CDROutIO))

-  val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) }
+  val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn with CDRInOverSample) }
+  when(true.B){
+    print("Warning!!! New Code has not been reviewed!\n")
+  }

  CDRIn(0).io.serDat  := cdrInio.dDatIn
  CDRIn(1).io.serDat  := cdrInio.uDatIn

-  CDRIn(0).io.overCLK := cdrInio.overCLK
-  CDRIn(1).io.overCLK := cdrInio.overCLK
+  CDRIn(0).overCLK := cdrInio.overCLK
+  CDRIn(1).overCLK := cdrInio.overCLK
+
+

  val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) }

--- a/src/main/scala/backBoard/ebus/TL2CDR.scala
+++ b/src/main/scala/backBoard/ebus/TL2CDR.scala
@@ -55,13 +55,16 @@ abstract class TL2CDRImplBase(outer: TL2CDR)(implicit p: Parameters) extends Laz
  val ( int, _ ) = outer.int_node.out(0)
  val ( bus, edge ) = outer.node.in.head

-  val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) }
+  val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn with CDRInOverSample) }
+  when(true.B){
+    print("Warning!!! New Code has not been reviewed!\n")
+  }

  CDRIn(0).io.serDat  := io.dDatIn
  CDRIn(1).io.serDat  := io.uDatIn

-  CDRIn(0).io.overCLK := io.overCLK
-  CDRIn(1).io.overCLK := io.overCLK
+  CDRIn(0).overCLK := io.overCLK
+  CDRIn(1).overCLK := io.overCLK

  val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) }

--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -5,7 +5,6 @@ import chisel3.util._


 class ShinTopIO extends Bundle{
-  val clk8x = Input(Bool())

  val dDatIn   = Input(Bool())
  val dDatOut  = Output(Bool())
@@ -56,18 +55,50 @@ class ShinTopIO extends Bundle{


 abstract class ShinTopBase extends Module{
+  def isMultiCLK: Int = 8
+
  val io: ShinTopIO = IO(new ShinTopIO)

-  // val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) }
-	// val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) }
+
+



 	val slaveParser  = Module(new SlaveParser )
 	val masterParser = Module(new MasterParser)

-  val downCDRIn  = Module(new CDRIn)
-  val upCDRIn    = Module(new CDRIn)
+  val ( downCDRIn, upCDRIn ) = 
+  if( isMultiCLK == 0 ){
+    val clk8x = IO(Input(Bool()))
+    val down = Module(new CDRIn with CDRInOverSample )
+    val up   = Module(new CDRIn with CDRInOverSample )
+    down.overCLK := clk8x
+    up.overCLK := clk8x
+    (down, up)
+  } else{
+    val multiCLK = IO(Input(Vec(isMultiCLK, Bool())))
+    val down = Module(new CDRIn with CDRInMultiSample)
+    val up   = Module(new CDRIn with CDRInMultiSample)
+    down.multiCLK := multiCLK
+    up.multiCLK   := multiCLK
+    (down, up)
+  }
+
+
+  // val downCDRIn  = if( isMultiCLK == 0 ) { Module(new CDRIn with CDRInOverSample ) } else { Module(new CDRIn with CDRInMultiSample) }
+  // val upCDRIn    = if( isMultiCLK == 0 ) { Module(new CDRIn with CDRInOverSample ) } else { Module(new CDRIn with CDRInMultiSample) }
+
+  // if( isMultiCLK == 0 ){
+  //   val clk8x = IO(Input(Bool()))
+  //   downCDRIn.overCLK := clk8x
+  //   upCDRIn.overCLK := clk8x
+  // } else {
+  //   val multiCLK = IO(Input(Vec(isMultiCLK, Bool())))
+  //   downCDRIn.multiCLK := multiCLK
+  //   upCDRIn.multiCLK := multiCLK
+  // }
+
+
  val downCDROut = Module(new CDROut)
  val upCDROut   = Module(new CDROut)

@@ -79,11 +110,9 @@ abstract class ShinTopBase extends Module{
  io.interrupt   := interface.io.interrupt

  downCDRIn.io.serDat  := io.dDatIn
-  downCDRIn.io.overCLK := io.clk8x
  downCDRIn.io.initEncryptor := interface.io.initEncryptor

  upCDRIn.io.serDat  := io.uDatIn
-  upCDRIn.io.overCLK := io.clk8x
  upCDRIn.io.initEncryptor := interface.io.initEncryptor

  io.dDatOut := downCDROut.io.serDat