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逻辑地址读转换修复

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Ruige Lee
2025-06-18 15:31:28 +08:00
parent 1579f4163a
commit 7c6056e047
1 changed files with 23 additions and 17 deletions
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40
src/main/scala/backBoard/shin/SlaveParser.scala
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@@ -428,15 +428,15 @@ trait SlaveParserRW{ this: SlaveParserBase =>
val isWRSM4 = (addrw(14,11) === "b0101".U) val isWRSM4 = (addrw(14,11) === "b0101".U)
val isWRSM6 = (addrw(14,11) === "b0111".U) val isWRSM6 = (addrw(14,11) === "b0111".U)
val downTransLenCnt = RegInit(0.U)
val isWrite = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相 val isWrite = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相
( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgInfo(0).isSeqIndex & downSubMsgInfo(0).devIndex === localDevIndex) || downSubMsgInfo(0).isLgcIndex) ) | ( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgInfo(0).isSeqIndex & downSubMsgInfo(0).devIndex === localDevIndex) || ( downSubMsgInfo(0).isLgcIndex & downTransLenCnt =/= 0.U) ) ) |
( isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgInfo(1).isSeqIndex & downSubMsgInfo(1).devIndex === localDevIndex) || downSubMsgInfo(1).isLgcIndex) ) | ( isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgInfo(1).isSeqIndex & downSubMsgInfo(1).devIndex === localDevIndex) || ( downSubMsgInfo(1).isLgcIndex & downTransLenCnt =/= 0.U) ) ) |
( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) | ( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) |
( isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) ( isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
) )
val downTransLenCnt = RegInit(0.U)
val isDownLgcAddrwAcquireTrans = //是否触发地址转换 val isDownLgcAddrwAcquireTrans = //是否触发地址转换
(downTransLenCnt === 0.U) & ( (0 until 8).map{ i => (downTransLenCnt === 0.U) & ( (0 until 8).map{ i =>
@@ -468,7 +468,10 @@ trait SlaveParserRW{ this: SlaveParserBase =>
(downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isLgcIndex (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isLgcIndex
)){//组合逻辑 )){//组合逻辑
logicAddrwNext := Cat( downRecParser.io.subMsgReq.bits.devIndex, downRecParser.io.subMsgReq.bits.address ) logicAddrwNext := Cat( downRecParser.io.subMsgReq.bits.devIndex, downRecParser.io.subMsgReq.bits.address )
} .elsewhen( isWrite & downRecParser.io.data.fire ){//组合逻辑 } .elsewhen( downRecParser.io.data.fire & (
( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgInfo(0).isLgcIndex ) |
( isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgInfo(1).isLgcIndex )
)){//组合逻辑
logicAddrwNext := logicAddrw + 1.U logicAddrwNext := logicAddrw + 1.U
} .otherwise{//组合逻辑 } .otherwise{//组合逻辑
logicAddrwNext := logicAddrw logicAddrwNext := logicAddrw
@@ -547,12 +550,13 @@ trait SlaveParserRW{ this: SlaveParserBase =>
val upTransLenCnt = RegInit(0.U)
//读出uSM //读出uSM
val isRead = val isRead =
((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( ((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & (
(~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(0).isSeqIndex & upSubMsgInfo(0).devIndex === localDevIndex) || upSubMsgInfo(0).isLgcIndex)) | (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(0).isSeqIndex & upSubMsgInfo(0).devIndex === localDevIndex) || (upSubMsgInfo(0).isLgcIndex & upTransLenCnt =/= 0.U ) )) |
( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(1).isSeqIndex & upSubMsgInfo(1).devIndex === localDevIndex) || upSubMsgInfo(1).isLgcIndex)) | ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(1).isSeqIndex & upSubMsgInfo(1).devIndex === localDevIndex) || (upSubMsgInfo(1).isLgcIndex & upTransLenCnt =/= 0.U ) )) |
(~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) | (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) |
( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR ) )
) )
@@ -562,28 +566,27 @@ trait SlaveParserRW{ this: SlaveParserBase =>
val logicAddrrNext = Wire( UInt(30.W) ) val logicAddrrNext = Wire( UInt(30.W) )
val logicAddrr = RegNext(logicAddrrNext) val logicAddrr = RegNext(logicAddrrNext)
val upTransLenCnt = RegInit(0.U)
val isUpLgcAddrwAcquireTrans = //是否触发地址转换 val isUpLgcAddrrAcquireTrans = //是否触发地址转换
(upTransLenCnt === 0.U) & ( (0 until 8).map{ i => (upTransLenCnt === 0.U) & ( (0 until 8).map{ i =>
sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr) sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrrNext === sReg.ebmmu(i).lAddr)
}.reduce(_|_)) }.reduce(_|_))
val acquireUpPhyAddrw = Mux1H( //选择一个ebmmu val acquireUpPhyAddrr = Mux1H( //选择一个ebmmu
(0 until 8).map{ i => (0 until 8).map{ i =>
(sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)) -> (sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrrNext === sReg.ebmmu(i).lAddr)) ->
sReg.ebmmu(i).pAddr sReg.ebmmu(i).pAddr
} }
) )
val acquireUpTransLen = Mux1H( //选择一个ebmmu val acquireUpTransLen = Mux1H( //选择一个ebmmu
(0 until 8).map{ i => (0 until 8).map{ i =>
(sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)) -> (sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrrNext === sReg.ebmmu(i).lAddr)) ->
sReg.ebmmu(i).length sReg.ebmmu(i).length
} }
) )
when( isUpLgcAddrwAcquireTrans ){ //装填计数器 when( isUpLgcAddrrAcquireTrans ){ //装填计数器
upTransLenCnt := acquireUpTransLen upTransLenCnt := acquireUpTransLen
} .elsewhen( upRecParser.io.data.fire & upTransLenCnt =/= 0.U){ } .elsewhen( upRecParser.io.data.fire & upTransLenCnt =/= 0.U){
upTransLenCnt := upTransLenCnt - 1.U upTransLenCnt := upTransLenCnt - 1.U
@@ -594,8 +597,11 @@ trait SlaveParserRW{ this: SlaveParserBase =>
(upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex
)){//组合逻辑 )){//组合逻辑
logicAddrrNext := Cat( upRecParser.io.subMsgReq.bits.devIndex, upRecParser.io.subMsgReq.bits.address ) logicAddrrNext := Cat( upRecParser.io.subMsgReq.bits.devIndex, upRecParser.io.subMsgReq.bits.address )
} .elsewhen( isRead & upRecParser.io.data.fire ){//组合逻辑 } .elsewhen( upRecParser.io.data.fire & (
logicAddrrNext := logicAddrw + 1.U (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(0).isLgcIndex ) |
( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(1).isLgcIndex )
) ){//组合逻辑
logicAddrrNext := logicAddrr + 1.U
} .otherwise{//组合逻辑 } .otherwise{//组合逻辑
logicAddrrNext := logicAddrr logicAddrrNext := logicAddrr
} }
@@ -617,7 +623,7 @@ trait SlaveParserRW{ this: SlaveParserBase =>
){ ){
addrr := upRecParser.io.subMsgReq.bits.address addrr := upRecParser.io.subMsgReq.bits.address
} .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){ } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){
addrr := acquireUpPhyAddrw addrr := acquireUpPhyAddrr
} }
} .elsewhen( isLvdsEnR ){ } .elsewhen( isLvdsEnR ){
when( when(
@@ -626,7 +632,7 @@ trait SlaveParserRW{ this: SlaveParserBase =>
){ ){
addrr := addrr + 1.U addrr := addrr + 1.U
} .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){ } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){
addrr := Mux( upTransLenCnt === 0.U, Mux(isUpLgcAddrwAcquireTrans, acquireUpPhyAddrw, 0.U), addrr + 1.U ) addrr := Mux( upTransLenCnt === 0.U, Mux(isUpLgcAddrrAcquireTrans, acquireUpPhyAddrr, 0.U), addrr + 1.U )
} }
} }