From 7c47137db7fbb53eb567f2d400fcd3b9164d734e Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Thu, 29 Jan 2026 17:46:15 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E6=94=B9bug=EF=BC=8Caddrr=E7=9A=84?= =?UTF-8?q?=E8=87=AA=E5=A2=9EbyteSel=E5=92=8Cenr=E7=9A=84byteSel?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/SpiInterface.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/backBoard/shin/SpiInterface.scala b/src/main/scala/backBoard/shin/SpiInterface.scala index 74339b5..bc43850 100644 --- a/src/main/scala/backBoard/shin/SpiInterface.scala +++ b/src/main/scala/backBoard/shin/SpiInterface.scala @@ -66,7 +66,7 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{ val spiCnt = RegInit(0.U(12.W)) io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(2) & bitSelNext.andR & isSpiWrite & byteSelNext >= 4.U & (spiCnt < spiLen) - io.isEnR := (isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 4.U ) & (spiCnt <= spiLen) + io.isEnR := (isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 3.U ) & (spiCnt <= spiLen) io.dataw := exRegi io.addrr := addrr @@ -104,7 +104,7 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{ } .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte addrr := Cat(addrr(7,0), exRegi(6,0), shiftMOSI) } .otherwise{ // byteSel > 1.U - when( isSckPosedge & byteSel >= 4.U & bitSel === 0.U ){ + when( isSckPosedge & byteSel >= 3.U & bitSel === 0.U ){ addrr := addrr + 1.U } }