diff --git a/src/main/scala/backBoard/shin/SpiInterface.scala b/src/main/scala/backBoard/shin/SpiInterface.scala
index 74339b5..bc43850 100644
--- a/src/main/scala/backBoard/shin/SpiInterface.scala
+++ b/src/main/scala/backBoard/shin/SpiInterface.scala
@@ -66,7 +66,7 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
   val spiCnt       = RegInit(0.U(12.W))
 
   io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(2) & bitSelNext.andR & isSpiWrite & byteSelNext >= 4.U & (spiCnt < spiLen)
-  io.isEnR := (isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 4.U ) & (spiCnt <= spiLen)
+  io.isEnR := (isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 3.U ) & (spiCnt <= spiLen)
 
   io.dataw := exRegi
   io.addrr := addrr
@@ -104,7 +104,7 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
   } .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
     addrr := Cat(addrr(7,0), exRegi(6,0), shiftMOSI)
   } .otherwise{ // byteSel > 1.U
-    when( isSckPosedge & byteSel >= 4.U & bitSel === 0.U ){
+    when( isSckPosedge & byteSel >= 3.U & bitSel === 0.U ){
       addrr := addrr + 1.U
     }
   }