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Merge branch 'ShinTop' into eb_dev

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This commit is contained in:
bacon
2025-05-23 12:57:13 +08:00
parent c1067f48e1 285e506b2a
commit 7b62f808d0
1 changed files with 26 additions and 18 deletions
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44
src/main/scala/backBoard/shin/SlaveParser.scala
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@@ -415,7 +415,12 @@ trait SlaveParserRW{ this: SlaveParserBase =>
( isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
)
when( downRecParser.io.subMsgReq.fire & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){
when( downRecParser.io.subMsgReq.fire & (
downRecParser.io.subMsgReq.bits.devIndex === localDevIndex |
downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE |
downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR
)
){
addrw := downRecParser.io.subMsgReq.bits.address
} .elsewhen( isWrite & downRecParser.io.data.fire ){
addrw := addrw + 1.U
@@ -497,7 +502,12 @@ trait SlaveParserRW{ this: SlaveParserBase =>
val isLvdsEnR = isRead & ( ((RegNext(upRecParser.io.stateCurr) =/= STATE_PAYLOAD_DATA) & (upRecParser.io.stateCurr === STATE_PAYLOAD_DATA)) |
upRecParser.io.data.fire )
when( upRecParser.io.subMsgReq.fire & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){
when( upRecParser.io.subMsgReq.fire & (
upRecParser.io.subMsgReq.bits.devIndex === localDevIndex |
upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD |
upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR
)
){
addrr := upRecParser.io.subMsgReq.bits.address
} .elsewhen( isLvdsEnR ){
addrr := addrr + 1.U
@@ -515,14 +525,13 @@ trait SlaveParserRW{ this: SlaveParserBase =>
when( ~isUpRecPing ){ //req fire 后 已经反相
upRecFifo(0).io.enq.valid := upRecParser.io.data.valid
upRecFifo(0).io.enq.bits :=
Mux( upSubMsgInfo(0).devIndex === localDevIndex & (
upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD |
upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR |
upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD |
upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR
),
upStreamData, upRecParser.io.data.bits)
upRecParser.io.data.ready := upRecFifo(0).io.enq.ready
Mux(
(( upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(0).devIndex === localDevIndex) |
( upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR )
,
upStreamData, upRecParser.io.data.bits
)
upRecParser.io.data.ready := upRecFifo(0).io.enq.ready
upRecFifo(1).io.enq.valid := false.B
upRecFifo(1).io.enq.bits := 0.U
@@ -532,14 +541,13 @@ trait SlaveParserRW{ this: SlaveParserBase =>
upRecFifo(1).io.enq.valid := upRecParser.io.data.valid
upRecFifo(1).io.enq.bits :=
Mux( upSubMsgInfo(1).devIndex === localDevIndex & (
upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD |
upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR |
upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD |
upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR
),
upStreamData, upRecParser.io.data.bits)
upRecParser.io.data.ready := upRecFifo(1).io.enq.ready
Mux(
(( upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(1).devIndex === localDevIndex) |
( upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR )
,
upStreamData, upRecParser.io.data.bits
)
upRecParser.io.data.ready := upRecFifo(1).io.enq.ready
}