diff --git a/src/main/scala/backBoard/ebus/b8b10.scala b/src/main/scala/backBoard/ebus/b8b10.scala
index 24d6701..9e87ead 100644
--- a/src/main/scala/backBoard/ebus/b8b10.scala
+++ b/src/main/scala/backBoard/ebus/b8b10.scala
@@ -21,38 +21,38 @@ class b8b10Encode extends Module with RequireAsyncReset{
 
 
   val b5b6LookUp = Mux1H(Seq(
-    (io.dataIn(4,0) === "b00000".U) -> Mux( rd, "b100111".U(6.W), "b011000".U(6.W) ),
-    (io.dataIn(4,0) === "b00001".U) -> Mux( rd, "b011101".U(6.W), "b100010".U(6.W) ),
-    (io.dataIn(4,0) === "b00010".U) -> Mux( rd, "b101101".U(6.W), "b010010".U(6.W) ),
+    (io.dataIn(4,0) === "b00000".U) -> Mux( ~rd, "b100111".U(6.W), "b011000".U(6.W) ),
+    (io.dataIn(4,0) === "b00001".U) -> Mux( ~rd, "b011101".U(6.W), "b100010".U(6.W) ),
+    (io.dataIn(4,0) === "b00010".U) -> Mux( ~rd, "b101101".U(6.W), "b010010".U(6.W) ),
     (io.dataIn(4,0) === "b00011".U) -> "b110001".U(6.W),
-    (io.dataIn(4,0) === "b00100".U) -> Mux( rd, "b110101".U(6.W), "b001010".U(6.W) ),
+    (io.dataIn(4,0) === "b00100".U) -> Mux( ~rd, "b110101".U(6.W), "b001010".U(6.W) ),
     (io.dataIn(4,0) === "b00101".U) -> "b101001".U(6.W),
     (io.dataIn(4,0) === "b00110".U) -> "b011001".U(6.W),
-    (io.dataIn(4,0) === "b00111".U) -> Mux( rd, "b111000".U(6.W), "b000111".U(6.W) ),
-    (io.dataIn(4,0) === "b01000".U) -> Mux( rd, "b111001".U(6.W), "b000110".U(6.W) ),
+    (io.dataIn(4,0) === "b00111".U) -> Mux( ~rd, "b111000".U(6.W), "b000111".U(6.W) ),
+    (io.dataIn(4,0) === "b01000".U) -> Mux( ~rd, "b111001".U(6.W), "b000110".U(6.W) ),
     (io.dataIn(4,0) === "b01001".U) -> "b100101".U(6.W),
     (io.dataIn(4,0) === "b01010".U) -> "b010101".U(6.W),
     (io.dataIn(4,0) === "b01011".U) -> "b110100".U(6.W),
     (io.dataIn(4,0) === "b01100".U) -> "b001101".U(6.W),
     (io.dataIn(4,0) === "b01101".U) -> "b101100".U(6.W),
     (io.dataIn(4,0) === "b01110".U) -> "b011100".U(6.W),
-    (io.dataIn(4,0) === "b01111".U) -> Mux( rd, "b010111".U(6.W), "b101000".U(6.W) ),
-    (io.dataIn(4,0) === "b10000".U) -> Mux( rd, "b011011".U(6.W), "b100100".U(6.W) ),
+    (io.dataIn(4,0) === "b01111".U) -> Mux( ~rd, "b010111".U(6.W), "b101000".U(6.W) ),
+    (io.dataIn(4,0) === "b10000".U) -> Mux( ~rd, "b011011".U(6.W), "b100100".U(6.W) ),
     (io.dataIn(4,0) === "b10001".U) -> "b100011".U(6.W),
     (io.dataIn(4,0) === "b10010".U) -> "b010011".U(6.W),
     (io.dataIn(4,0) === "b10011".U) -> "b110010".U(6.W),
     (io.dataIn(4,0) === "b10100".U) -> "b001011".U(6.W),
     (io.dataIn(4,0) === "b10101".U) -> "b101010".U(6.W),
     (io.dataIn(4,0) === "b10110".U) -> "b011010".U(6.W),
-    (io.dataIn(4,0) === "b10111".U) -> Mux( rd, "b111010".U(6.W), "b000101".U(6.W) ),
-    (io.dataIn(4,0) === "b11000".U) -> Mux( rd, "b110011".U(6.W), "b001100".U(6.W) ),
+    (io.dataIn(4,0) === "b10111".U) -> Mux( ~rd, "b111010".U(6.W), "b000101".U(6.W) ),
+    (io.dataIn(4,0) === "b11000".U) -> Mux( ~rd, "b110011".U(6.W), "b001100".U(6.W) ),
     (io.dataIn(4,0) === "b11001".U) -> "b100110".U(6.W),
     (io.dataIn(4,0) === "b11010".U) -> "b010110".U(6.W),
-    (io.dataIn(4,0) === "b11011".U) -> Mux( rd, "b110110".U(6.W), "b001001".U(6.W) ),
+    (io.dataIn(4,0) === "b11011".U) -> Mux( ~rd, "b110110".U(6.W), "b001001".U(6.W) ),
     (io.dataIn(4,0) === "b11100".U) -> "b001110".U(6.W),
-    (io.dataIn(4,0) === "b11101".U) -> Mux( rd, "b101110".U(6.W), "b010001".U(6.W) ),
-    (io.dataIn(4,0) === "b11110".U) -> Mux( rd, "b011110".U(6.W), "b100001".U(6.W) ),
-    (io.dataIn(4,0) === "b11111".U) -> Mux( rd, "b101011".U(6.W), "b010100".U(6.W) )
+    (io.dataIn(4,0) === "b11101".U) -> Mux( ~rd, "b101110".U(6.W), "b010001".U(6.W) ),
+    (io.dataIn(4,0) === "b11110".U) -> Mux( ~rd, "b011110".U(6.W), "b100001".U(6.W) ),
+    (io.dataIn(4,0) === "b11111".U) -> Mux( ~rd, "b101011".U(6.W), "b010100".U(6.W) )
   ))
 
 
@@ -92,14 +92,14 @@ class b8b10Encode extends Module with RequireAsyncReset{
   ))
 
   val b3b4LookUp = Mux1H(Seq(
-    (io.dataIn(7,5) === "b000".U) -> Mux( b5b6RD, "b1011".U(4.W), "b0100".U(4.W) ),
+    (io.dataIn(7,5) === "b000".U) -> Mux( ~b5b6RD, "b1011".U(4.W), "b0100".U(4.W) ),
     (io.dataIn(7,5) === "b001".U) -> "b1001".U(4.W),
     (io.dataIn(7,5) === "b010".U) -> "b0101".U(4.W),
-    (io.dataIn(7,5) === "b011".U) -> Mux( b5b6RD, "b1100".U(4.W), "b0011".U(4.W) ),
-    (io.dataIn(7,5) === "b100".U) -> Mux( b5b6RD, "b1101".U(4.W), "b0010".U(4.W) ),
+    (io.dataIn(7,5) === "b011".U) -> Mux( ~b5b6RD, "b1100".U(4.W), "b0011".U(4.W) ),
+    (io.dataIn(7,5) === "b100".U) -> Mux( ~b5b6RD, "b1101".U(4.W), "b0010".U(4.W) ),
     (io.dataIn(7,5) === "b101".U) -> "b1010".U(4.W),
     (io.dataIn(7,5) === "b110".U) -> "b0110".U(4.W),
-    (io.dataIn(7,5) === "b111".U) -> MuxCase( Mux( b5b6RD, "b1110".U(4.W), "b0001".U(4.W) ), Array(
+    (io.dataIn(7,5) === "b111".U) -> MuxCase( Mux( ~b5b6RD, "b1110".U(4.W), "b0001".U(4.W) ), Array(
       ((io.dataIn(4,0) === 17.U || io.dataIn(4,0) === 18.U || io.dataIn(4,0) === 20.U) & ~b5b6RD) -> "b0111".U(4.W),  // 17, 18, 20 are special cases
       ((io.dataIn(4,0) === 11.U || io.dataIn(4,0) === 13.U || io.dataIn(4,0) === 14.U) &  b5b6RD) -> "b1000".U(4.W),  // 11, 13, 14 are special cases 
     ))