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同步和probe写完

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This commit is contained in:
Ruige Lee
2025-04-22 17:32:05 +08:00
parent 58eb3c0aed
commit 7afd4a1249
2 changed files with 246 additions and 196 deletions
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434
src/main/scala/backBoard/shin/SlaveParser.scala
View File

@@ -7,6 +7,7 @@ import chisel3.util._
class FrameHeader extends Bundle{
val frameLenAim = UInt(12.W) //帧长度目标
val frameStyle = UInt(2.W) //包类型
val frameInfo = UInt(16.W) //其它信息，如probe
}
class SubMsgHeader extends Bundle{
@@ -84,7 +85,6 @@ abstract class SlaveParserBase extends Module{
// val upSinkSel = Reg(Bool())
val downFrameInfo = Reg(new FrameHeader) //下行大包头
val upFrameInfo = Reg(new FrameHeader) //上行大包头
// val isDownSendBusy = downSendGen.io.frameReq.ready
@@ -96,11 +96,6 @@ abstract class SlaveParserBase extends Module{
// val isUpProbePending
//处理主报文
// when(downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE){ //下行来了一个嗅探包
// // isUpSendPend := true.B //嗅探包不会立即发送，而是看门狗形式
// //downFrameInfo := downRecParser.io.frameReq.bits
// } .elsewhen( ){
when( downSendGen.io.frameReq.fire ){
isDownSendPend := false.B
@@ -109,9 +104,6 @@ abstract class SlaveParserBase extends Module{
downFrameInfo := downRecParser.io.frameReq.bits
}
// when( upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE){ //上行来了一个嗅探包
// println("Probe Resp!")
when( upSendGen.io.frameReq.fire ){
isUpSendPend := false.B
} .elsewhen( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){ //上行来了一个普通包
@@ -138,17 +130,20 @@ abstract class SlaveParserBase extends Module{
))
val upFrameProbeInfo: FrameHeader = Wire(new FrameHeader)
upFrameProbeInfo.frameLenAim := 0.U //帧长度目标
upFrameProbeInfo.frameStyle := FRAME_STYLE_PROBE //包类型
upFrameProbeInfo.frameInfo := localDevIndex //其它信息，如probe
upSendGen.io.frameReq.valid :=
isUpSendPend & upRecParser.io.subMsgReq.fire //| 上行转发
//isUpSendProbe | // 上行探针
isUpSendPend & upRecParser.io.subMsgReq.fire | //上行转发
isReadyToProbe // 上行探针
// assert( OneHot(isUpSendPend, isUpSendProbe) )
assert( ~(isUpSendPend & isUpSendProbe), "Assert Failed, Check Softwave, Probe is Sent while transfering!\n" )
upSendGen.io.frameReq.bits := Mux1H(Seq(
isUpSendPend -> upFrameInfo, //上行转发
//isUpSendProbe -> probeFrame, //上行探针
isReadyToProbe -> upFrameProbeInfo, //上行探针
))
@@ -192,20 +187,6 @@ abstract class SlaveParserBase extends Module{
downSubMsgInfo(0).length := downRecParser.io.subMsgReq.bits.length
downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt
downSubMsgInfo(0).source := 0.U
//override
when( downRecParser.io.subMsgReq.bits.devIndex === localDevIndex & ( (downRecParser.io.subMsgReq.bits.operator === 1.U) | (downRecParser.io.subMsgReq.bits.operator === 3.U) ) ) { //自身包//写操作或读写操作)
downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
}
when(
downRecParser.io.subMsgReq.bits.devIndex === 0.U &
downRecParser.io.subMsgReq.bits.style === 0.U &
downRecParser.io.subMsgReq.bits.operator === "hd".U ){ //设置顺序地址
localDevIndex := downRecParser.io.subMsgReq.bits.workCnt + 1.U
downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
}
} .otherwise{ //pong
downSubMsgInfo(1).devIndex := downRecParser.io.subMsgReq.bits.devIndex
downSubMsgInfo(1).style := downRecParser.io.subMsgReq.bits.style
@@ -214,20 +195,6 @@ abstract class SlaveParserBase extends Module{
downSubMsgInfo(1).length := downRecParser.io.subMsgReq.bits.length
downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt
downSubMsgInfo(1).source := 1.U
//override
when( downRecParser.io.subMsgReq.bits.devIndex === localDevIndex & ( (downRecParser.io.subMsgReq.bits.operator === 1.U) | (downRecParser.io.subMsgReq.bits.operator === 3.U) )) { //自身包//写操作或读写操作 )
downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
}
when(
downRecParser.io.subMsgReq.bits.devIndex === 0.U &
downRecParser.io.subMsgReq.bits.style === 0.U &
downRecParser.io.subMsgReq.bits.operator === "hd".U ){ //设置顺序地址
localDevIndex := downRecParser.io.subMsgReq.bits.workCnt + 1.U
downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
}
}
}
@@ -251,6 +218,165 @@ abstract class SlaveParserBase extends Module{
downRecParser.io.data.ready := downRecFifo(1).io.enq.ready
}
//上行接收
when( upRecParser.io.subMsgReq.fire ){
when( isUpRecPing ){
upSubMsgInfo(0).devIndex := upRecParser.io.subMsgReq.bits.devIndex
upSubMsgInfo(0).style := upRecParser.io.subMsgReq.bits.style
upSubMsgInfo(0).address := upRecParser.io.subMsgReq.bits.address
upSubMsgInfo(0).operator := upRecParser.io.subMsgReq.bits.operator
upSubMsgInfo(0).length := upRecParser.io.subMsgReq.bits.length
upSubMsgInfo(0).workCnt := upRecParser.io.subMsgReq.bits.workCnt
upSubMsgInfo(0).source := 0.U
} .otherwise{
upSubMsgInfo(1).devIndex := upRecParser.io.subMsgReq.bits.devIndex
upSubMsgInfo(1).style := upRecParser.io.subMsgReq.bits.style
upSubMsgInfo(1).address := upRecParser.io.subMsgReq.bits.address
upSubMsgInfo(1).operator := upRecParser.io.subMsgReq.bits.operator
upSubMsgInfo(1).length := upRecParser.io.subMsgReq.bits.length
upSubMsgInfo(1).workCnt := upRecParser.io.subMsgReq.bits.workCnt
upSubMsgInfo(1).source := 1.U
}
}
//子报文下行发送
val isDownSendPing = RegInit(false.B)
val isUpSendPing = RegInit(false.B)
downSendGen.io.subMsgReq.valid :=
( isDownSendPing & isDownSubMsgValid(0) ) | (~isDownSendPing & isDownSubMsgValid(1))
downSendGen.io.subMsgReq.bits := Mux( isDownSendPing, downSubMsgInfo(0), downSubMsgInfo(1) )
when( downSendGen.io.subMsgReq.fire ){ //ready
isDownSendPing := ~isDownSendPing
when( isDownSendPing ){
assert( isDownSubMsgValid(0) )
isDownSubMsgValid(0) := false.B
} .otherwise{
assert( isDownSubMsgValid(1) )
isDownSubMsgValid(1) := false.B
}
} .elsewhen( downRecParser.io.subMsgReq.fire ){
isDownRecPing := ~isDownRecPing
when( isDownRecPing ){
assert( ~isDownSubMsgValid(0) )
isDownSubMsgValid(0) := true.B
} .otherwise{
assert( ~isDownSubMsgValid(1) )
isDownSubMsgValid(1) := true.B
}
}
downRecFifo(0).io.deq <> downSendGen.io.data(0)
downRecFifo(1).io.deq <> downSendGen.io.data(1)
downRecParser.io.resp := ( downRecParser.io.stateCurr === STATE_WAIT ) & (~isDownSubMsgValid(0) & ~isDownSubMsgValid(1))
//子报文上行发送
upSendGen.io.subMsgReq.valid :=
( isUpSendPing & isUpSubMsgValid(0) ) |
( ~isUpSendPing & isUpSubMsgValid(1) )
upSendGen.io.subMsgReq.bits := Mux( isUpSendPing, upSubMsgInfo(0), upSubMsgInfo(1) )
when( upSendGen.io.subMsgReq.fire ){ //ready
isUpSendPing := ~isUpSendPing
when( isUpSendPing ){
assert( isUpSubMsgValid(0) )
isUpSubMsgValid(0) := false.B
} .otherwise{
assert( isUpSubMsgValid(1) )
isUpSubMsgValid(1) := false.B
}
}.elsewhen( upRecParser.io.subMsgReq.fire ){
isUpRecPing := ~isUpRecPing
when( isUpRecPing ){
assert( ~isUpSubMsgValid(0) )
isUpSubMsgValid(0) := true.B
} .otherwise{
assert( ~isUpSubMsgValid(1) )
isUpSubMsgValid(1) := true.B
}
}
upRecFifo(0).io.deq <> upSendGen.io.data(0)
upRecFifo(1).io.deq <> upSendGen.io.data(1)
upRecParser.io.resp := ( upRecParser.io.stateCurr === STATE_WAIT ) & (~isUpSubMsgValid(0) & ~isUpSubMsgValid(1))
}
trait SlaveParserIndex{ this: SlaveParserBase =>
//下行接收
when( downRecParser.io.subMsgReq.fire &
downRecParser.io.subMsgReq.bits.devIndex === 0.U &
downRecParser.io.subMsgReq.bits.style === 0.U &
downRecParser.io.subMsgReq.bits.operator === "hd".U ){ //设置顺序地址
localDevIndex := downRecParser.io.subMsgReq.bits.workCnt + 1.U
isDeviceModified := false.B
when( isDownRecPing ){
downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
} .otherwise{ //pong
downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
}
}
}
trait SlaveParserRW{ this: SlaveParserBase =>
//下行接收
when( downRecParser.io.subMsgReq.fire ){
when( isDownRecPing ){
//override
when( downRecParser.io.subMsgReq.bits.devIndex === localDevIndex & ( (downRecParser.io.subMsgReq.bits.operator === 1.U) | (downRecParser.io.subMsgReq.bits.operator === 3.U) ) ) { //自身包//写操作或读写操作)
downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
}
} .otherwise{ //pong
//override
when( downRecParser.io.subMsgReq.bits.devIndex === localDevIndex & ( (downRecParser.io.subMsgReq.bits.operator === 1.U) | (downRecParser.io.subMsgReq.bits.operator === 3.U) )) { //自身包//写操作或读写操作 )
downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
}
}
}
//写入SM
val addrw = Reg(UInt(15.W))
@@ -294,42 +420,30 @@ abstract class SlaveParserBase extends Module{
//上行接收
when( upRecParser.io.subMsgReq.fire ){
when( isUpRecPing ){
upSubMsgInfo(0).devIndex := upRecParser.io.subMsgReq.bits.devIndex
upSubMsgInfo(0).style := upRecParser.io.subMsgReq.bits.style
upSubMsgInfo(0).address := upRecParser.io.subMsgReq.bits.address
upSubMsgInfo(0).operator := upRecParser.io.subMsgReq.bits.operator
upSubMsgInfo(0).length := upRecParser.io.subMsgReq.bits.length
upSubMsgInfo(0).workCnt := upRecParser.io.subMsgReq.bits.workCnt
upSubMsgInfo(0).source := 0.U
//override
when( upRecParser.io.subMsgReq.bits.devIndex === localDevIndex & ( (upRecParser.io.subMsgReq.bits.operator === 2.U) || (upRecParser.io.subMsgReq.bits.operator === 3.U) ) ){ //自身包//读或读写
upSubMsgInfo(0).workCnt := upRecParser.io.subMsgReq.bits.workCnt + 1.U
}
} .otherwise{
upSubMsgInfo(1).devIndex := upRecParser.io.subMsgReq.bits.devIndex
upSubMsgInfo(1).style := upRecParser.io.subMsgReq.bits.style
upSubMsgInfo(1).address := upRecParser.io.subMsgReq.bits.address
upSubMsgInfo(1).operator := upRecParser.io.subMsgReq.bits.operator
upSubMsgInfo(1).length := upRecParser.io.subMsgReq.bits.length
upSubMsgInfo(1).workCnt := upRecParser.io.subMsgReq.bits.workCnt
upSubMsgInfo(1).source := 1.U
//override
when( upRecParser.io.subMsgReq.bits.devIndex === localDevIndex & ( (upRecParser.io.subMsgReq.bits.operator === 2.U) || (upRecParser.io.subMsgReq.bits.operator === 3.U) )){ //自身包//读或读写 )
upSubMsgInfo(1).workCnt := upRecParser.io.subMsgReq.bits.workCnt + 1.U
}
}
}
}
}
//读出uSM
val isReadSM =
((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & (upSubMsgInfo(0).devIndex === localDevIndex) & (upSubMsgInfo(0).operator === 2.U | upSubMsgInfo(0).operator === 3.U)) |
((upRecParser.io.stateNext === STATE_PAYLOAD_DATA) & (upRecParser.io.subMsgReq.bits.devIndex === localDevIndex) & (upRecParser.io.subMsgReq.bits.operator === 2.U | upRecParser.io.subMsgReq.bits.operator === 3.U))
@@ -380,112 +494,9 @@ abstract class SlaveParserBase extends Module{
io.uSMdeq(2).ready := isReadSM & ( upRecParser.io.stateNext === STATE_PAYLOAD_DATA ) & ( readSMAddr === 2.U )
io.uSMdeq(3).ready := isReadSM & ( upRecParser.io.stateNext === STATE_PAYLOAD_DATA ) & ( readSMAddr === 3.U )
}
//子报文下行发送
val isDownSendPing = RegInit(false.B)
val isUpSendPing = RegInit(false.B)
val isLastDevice: Bool = false.B
downSendGen.io.subMsgReq.valid :=
( isDownSendPing & isDownSubMsgValid(0) ) | (~isDownSendPing & isDownSubMsgValid(1))
downSendGen.io.subMsgReq.bits := Mux( isDownSendPing, downSubMsgInfo(0), downSubMsgInfo(1) )
when( downSendGen.io.subMsgReq.fire ){ //ready
isDownSendPing := ~isDownSendPing
when( isDownSendPing ){
assert( isDownSubMsgValid(0) )
isDownSubMsgValid(0) := false.B
} .otherwise{
assert( isDownSubMsgValid(1) )
isDownSubMsgValid(1) := false.B
}
} .elsewhen( downRecParser.io.subMsgReq.fire ){
isDownRecPing := ~isDownRecPing
when( isDownRecPing ){
assert( ~isDownSubMsgValid(0) )
isDownSubMsgValid(0) := true.B
} .otherwise{
assert( ~isDownSubMsgValid(1) )
isDownSubMsgValid(1) := true.B
}
}
downRecFifo(0).io.deq <> downSendGen.io.data(0)
downRecFifo(1).io.deq <> downSendGen.io.data(1)
downRecParser.io.resp := ( downRecParser.io.stateCurr === STATE_WAIT ) & (~isDownSubMsgValid(0) & ~isDownSubMsgValid(1))
//子报文上行发送
upSendGen.io.subMsgReq.valid :=
( isUpSendPing & isUpSubMsgValid(0) ) | (~isUpSendPing & isUpSubMsgValid(1))
upSendGen.io.subMsgReq.bits := Mux( isUpSendPing, upSubMsgInfo(0), upSubMsgInfo(1) )
when( upSendGen.io.subMsgReq.fire ){ //ready
isUpSendPing := ~isUpSendPing
when( isUpSendPing ){
assert( isUpSubMsgValid(0) )
isUpSubMsgValid(0) := false.B
} .otherwise{
assert( isUpSubMsgValid(1) )
isUpSubMsgValid(1) := false.B
}
}.elsewhen( upRecParser.io.subMsgReq.fire ){
isUpRecPing := ~isUpRecPing
when( isUpRecPing ){
assert( ~isUpSubMsgValid(0) )
isUpSubMsgValid(0) := true.B
} .otherwise{
assert( ~isUpSubMsgValid(1) )
isUpSubMsgValid(1) := true.B
}
}
upRecFifo(0).io.deq <> upSendGen.io.data(0)
upRecFifo(1).io.deq <> upSendGen.io.data(1)
upRecParser.io.resp := ( upRecParser.io.stateCurr === STATE_WAIT ) & (~isUpSubMsgValid(0) & ~isUpSubMsgValid(1))
val isReadyToProbe = RegInit(false.B)
io.upOut <> upSendGen.io.send
io.downIn <> downRecParser.io.rec
when( isLastDevice & isReadyToProbe ){
downSendGen.io.send <> upRecParser.io.rec
io.downOut.valid := false.B
io.downOut.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
io.upIn.ready := false.B
} .otherwise{
io.downOut <> downSendGen.io.send
io.upIn <> upRecParser.io.rec
}
trait SlaveParserSync{ this: SlaveParserBase =>
val downTimeStamp = Reg(UInt(64.W)) //下行本地时间戳寄存器
val upTimeStamp = Reg(UInt(64.W)) //下行本地时间戳寄存器
@@ -494,11 +505,16 @@ trait SlaveParserSync{ this: SlaveParserBase =>
val slvDeltaTimeStamp = Reg(UInt(32.W)) //从站时间戳差值
val mstSlvDeltaTimeStamp = Reg(UInt(32.W)) //主发从接时间差(中间变量)
val deltaMstSlvDeltaTimeStamp = Reg(UInt(32.W)) //主差从差时间差(中间变量)
val deltaFinal = Reg(UInt(32.W)) //当前时间戳与主站时间差
val recoTimeStamp = Reg(UInt(64.W)) //时钟补偿寄存器
recoTimeStamp = io.timeStamp + (mstSlvDeltaTimeStamp) + (mstDeltaTimeStamp - slvDeltaTimeStamp) >> 1
// recoTimeStamp = io.timeStamp + deltaFinal
// recoTimeStamp = io.timeStamp + mstSlvDeltaTimeStamp + deltaMstSlvDeltaTimeStamp
// recoTimeStamp = io.timeStamp + mstTimeStamp - downTimeStamp + (mstDeltaTimeStamp - slvDeltaTimeStamp ) >> 1
// recoTimeStamp = io.timeStamp + mstTimeStamp - downTimeStamp + (mstDeltaTimeStamp - (upTimeStamp - downTimeStamp)) >> 1
//更新下行本地时间戳寄存器
@@ -557,42 +573,72 @@ trait SlaveParserSync{ this: SlaveParserBase =>
}
}
io.dSMenq(0).valid := isWriteSM & addrw === 0.U
io.dSMenq(0).bits := downRecParser.io.data.bits
when( io.dSMenq(0).valid & ~io.dSMenq(0).ready ){
printf("An Error occur at dSMenq0!\n")
when( RegNext(isSync) & ~isSync ){
deltaMstSlvDeltaTimeStamp := (mstDeltaTimeStamp - slvDeltaTimeStamp) >> 1
} .elsewhen( RegNext(RegNext(isSync)) & ~RegNext(isSync) ){
deltaFinal := mstSlvDeltaTimeStamp + deltaMstSlvDeltaTimeStamp
}
io.dSMenq(1).valid := isWriteSM & addrw === 1.U
io.dSMenq(1).bits := downRecParser.io.data.bits
when( io.dSMenq(1).valid & ~io.dSMenq(1).ready ){
printf("An Error occur at dSMenq1!\n")
}
io.dSMenq(2).valid := isWriteSM & addrw === 2.U
io.dSMenq(2).bits := downRecParser.io.data.bits
when( io.dSMenq(2).valid & ~io.dSMenq(2).ready ){
printf("An Error occur at dSMenq2!\n")
}
io.dSMenq(3).valid := isWriteSM & addrw === 3.U
io.dSMenq(3).bits := downRecParser.io.data.bits
when( io.dSMenq(3).valid & ~io.dSMenq(3).ready ){
printf("An Error occur at dSMenq3!\n")
}
}
trait SlaveParserProbe{ this: SlaveParserBase =>
val ProbeSendAim = 10000.U
val ProbeRecAim = 20000.U
val probeSendCnt = RegInit(0.U(32.W))
val probeRecCnt = RegInit(0.U(32.W))
val isReadyToProbe = probeSendCnt === ProbeSendAim
val isWatchDogOverflow = probeRecCnt === ProbeRecAim
val isLastDevice: Bool = RegInit(false.B)
val isDeviceModified: Bool = RegInit(true.B)
when( upRecParser.io.frameReq.fire ){ //上行来了一个嗅探包
probeRecCnt := 0.U
isLastDevice := false.B
} .elsewhen( isWatchDogOverflow ){
probeRecCnt := 0.U
isLastDevice := true.B
} .otherwise{
probeRecCnt := probeRecCnt + 1.U
}
when( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行来了一个嗅探包
when( upRecParser.io.frameReq.bits.frameInfo =/= localDevIndex + 1.U ){
isDeviceModified := true.B
}
}
io.upOut <> upSendGen.io.send
io.downIn <> downRecParser.io.rec
when( isLastDevice & isReadyToProbe ){
downSendGen.io.send <> upRecParser.io.rec
io.downOut.valid := false.B
io.downOut.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
io.upIn.ready := false.B
} .otherwise{
io.downOut <> downSendGen.io.send
io.upIn <> upRecParser.io.rec
}
}
class SlaveParser extends SlaveParserBase
with SlaveParserIndex
with SlaveParserRW
with SlaveParserSync
with SlaveParserProbe

6
src/main/scala/backBoard/shin/SlaveRecParser.scala
View File

@@ -131,6 +131,10 @@ class SlaveRecParser extends Module{
} .elsewhen( stateCurr === STATE_HEADER & lengthCnt === 1.U ){
frameHeader.frameLenAim := frameHeader.frameLenAim | io.rec.bits.tdata(7,4)
frameHeader.frameStyle := io.rec.bits.tdata(1,0)
} .elsewhen( stateCurr === STATE_HEADER & lengthCnt === 2.U ){
frameHeader.frameInfo := io.rec.bits.tdata << 8
} .elsewhen( stateCurr === STATE_HEADER & lengthCnt === 3.U ){
frameHeader.frameInfo := frameHeader.frameInfo | io.rec.bits.tdata
}
when( stateCurr === STATE_PAYLOAD_INDEX_STYLE & lengthCnt === 0.U ){
@@ -165,7 +169,7 @@ class SlaveRecParser extends Module{
//必须使用上升沿触发，以避免前一帧长度超过预期
( stateCurr === STATE_IDLE ) -> Mux( ~RegNext(io.rec.valid) & io.rec.valid, STATE_HEADER, STATE_IDLE ),
( stateCurr === STATE_HEADER ) -> Mux( isShortRx, STATE_ERROR,
Mux( lengthCnt === 0.U, STATE_HEADER,
Mux( lengthCnt =/= (4-1).U, STATE_HEADER,
MuxCase( STATE_ERROR, Array(
( io.rec.bits.tdata(1,0) === FRAME_STYLE_COMMON ) -> STATE_PAYLOAD_INDEX_STYLE,
( io.rec.bits.tdata(1,0) === FRAME_STYLE_PROBE ) -> STATE_CRC,