From 79c3364492a55e27e5e6a13582d920922d98195b Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Mon, 30 Jun 2025 15:11:29 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E5=A4=8Daddrw=E5=9C=A8=E9=80=BB?= =?UTF-8?q?=E8=BE=91=E5=AF=BB=E5=9D=80=E4=B8=8B=E7=9A=84=E6=93=8D=E4=BD=9C?= =?UTF-8?q?=E9=80=BB=E8=BE=91?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../scala/backBoard/shin/SlaveParser.scala | 52 +++++++++---------- 1 file changed, 25 insertions(+), 27 deletions(-) diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index 03aeb67..d91c21e 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -562,30 +562,30 @@ trait SlaveParserRW{ this: SlaveParserBase => logicAddrwNext := logicAddrw } - - when( downRecParser.io.subMsgHeadReq.fire ){ //子包头装填 - when( - ( (downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgHeadReq.bits.isSeqIndex & downRecParser.io.subMsgHeadReq.bits.devIndex === localDevIndex ) | - ( downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR ) - ){ //常规寻址 + when( + ( (downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgHeadReq.bits.isSeqIndex & downRecParser.io.subMsgHeadReq.bits.devIndex === localDevIndex ) | + ( downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR ) + ){ //常规寻址 + when( downRecParser.io.subMsgHeadReq.fire ){ //子包头装填 addrw := downRecParser.io.subMsgHeadReq.bits.address - } .elsewhen( (downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgHeadReq.bits.isLgcIndex ){ //逻辑寻址 - addrw := acquireDownPhyAddrw - } - } .elsewhen( isWrite & downRecParser.io.data.fire ){ - when( - ( (downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgHeadReq.bits.isSeqIndex & downRecParser.io.subMsgHeadReq.bits.devIndex === localDevIndex ) | - ( downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR ) - ){ + } .elsewhen( isWrite & downRecParser.io.data.fire ){ addrw := addrw + 1.U - } .elsewhen( (downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgHeadReq.bits.isLgcIndex ){ - addrw := Mux( downTransLenCnt === 0.U, Mux(isDownLgcAddrwAcquireTrans, acquireDownPhyAddrw, 0.U), addrw + 1.U ) } + } .elsewhen( isDownLgcAddrwAcquireTrans & ( + ( downRecParser.io.subMsgHeadReq.fire & (downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgHeadReq.bits.isLgcIndex ) | + ( isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(0).isLgcIndex ) | + ( ~isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(1).isLgcIndex ) + )){ + addrw := acquireDownPhyAddrw + } .elsewhen( + isWrite & downRecParser.io.data.fire & ( + ( isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(0).isLgcIndex ) | + ( ~isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(1).isLgcIndex ) + ) ){ + assert(~isDownLgcAddrwAcquireTrans) + addrw := Mux( downTransLenCnt === 0.U, 0.U, addrw + 1.U ) } - - - io.lvds.isEnW := isWrite & isWRReg & downRecParser.io.data.fire io.lvds.dataw := downRecParser.io.data.bits @@ -731,14 +731,12 @@ trait SlaveParserRW{ this: SlaveParserBase => } .elsewhen(isLvdsEnR){ addrr := addrr + 1.U } - } .elsewhen( isUpLgcAddrrAcquireTrans ){ - when( - (upRecParser.io.subMsgHeadReq.fire & (upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgHeadReq.bits.isLgcIndex) | - ( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) | - (~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex )) - ){ - addrr := acquireUpPhyAddrr - } + } .elsewhen( isUpLgcAddrrAcquireTrans & ( + (upRecParser.io.subMsgHeadReq.fire & (upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgHeadReq.bits.isLgcIndex) | + ( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) | + (~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex )) + )){ + addrr := acquireUpPhyAddrr } .elsewhen( isLvdsEnR & ( ( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) | (~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex ))