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编译通过 仿真启动 请知悉 改处理器没有csr

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This commit is contained in:
RuigeLee
2024-10-25 17:46:21 +08:00
parent 4737700f56
commit 78d54d2083
20 changed files with 880 additions and 69 deletions
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10
Makefile
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@@ -60,22 +60,22 @@ test:
sw: sw:
riscv64-unknown-elf-gcc -Os -ggdb -march=rv32im -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs \ riscv64-unknown-elf-gcc -Os -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs \
-I ./tb/sw/ -I ./tb/sw/src -I ./tb/sw/axi_gpio -I ./tb/sw/axi_uart -I ./tb/sw/axi_timer \ -I ./tb/sw/ -I ./tb/sw/src -I ./tb/sw/axi_gpio -I ./tb/sw/axi_uart -I ./tb/sw/axi_timer \
-c ./tb/sw/src/main.c \ -c ./tb/sw/src/main.c \
-o ./tb/sw/build/main.o -o ./tb/sw/build/main.o
riscv64-unknown-elf-gcc -Os -ggdb -march=rv32im -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs \ riscv64-unknown-elf-gcc -Os -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs \
-I ./tb/sw/ -I ./tb/sw/src -I ./tb/sw/axi_gpio -I ./tb/sw/axi_uart -I ./tb/sw/axi_timer \ -I ./tb/sw/ -I ./tb/sw/src -I ./tb/sw/axi_gpio -I ./tb/sw/axi_uart -I ./tb/sw/axi_timer \
-c ./tb/sw/axi_uart/uart.c \ -c ./tb/sw/axi_uart/uart.c \
-o ./tb/sw/build/uart.o -o ./tb/sw/build/uart.o
riscv64-unknown-elf-gcc -Os -ggdb -march=rv32im -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \ riscv64-unknown-elf-gcc -Os -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
-I ./tb/sw/ -I ./tb/sw/src -I ./tb/sw/axi_gpio -I ./tb/sw/axi_uart -I ./tb/sw/axi_timer \ -I ./tb/sw/ -I ./tb/sw/src -I ./tb/sw/axi_gpio -I ./tb/sw/axi_uart -I ./tb/sw/axi_timer \
-c ./tb/sw/src/startup.S \ -c ./tb/sw/src/startup.S \
-o ./tb/sw/build/startup.o -o ./tb/sw/build/startup.o
riscv64-unknown-elf-gcc -Os -ggdb -march=rv32im -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles \ riscv64-unknown-elf-gcc -Os -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles \
-T ./tb/sw/linker.lds \ -T ./tb/sw/linker.lds \
./tb/sw/build/startup.o \ ./tb/sw/build/startup.o \
./tb/sw/build/uart.o \ ./tb/sw/build/uart.o \
@@ -125,7 +125,7 @@ tb:
-I ./tb \ -I ./tb \
-I ./generated/cdr/ \ -I ./generated/cdr/ \
-D RANDOMIZE_REG_INIT \ -D RANDOMIZE_REG_INIT \
./tb/ShinBack_tb.v ./tb/backSys_tb.v
vvp -N ./build/wave.iverilog -lxt2 vvp -N ./build/wave.iverilog -lxt2
vcd: vcd:

14
build.sbt
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@@ -97,11 +97,25 @@ lazy val rocketchip = freshProject("rocketchip", file("./rocket-chip"))
) )
lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies) lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies)
lazy val blocks = (project in file("./rocket-chip-blocks"))
.dependsOn(rocketchip)
.settings(chiselSettings)
.settings(commonSettings)
.settings(name := "blocks", organization := "org.chipsalliance")
.settings(
libraryDependencies ++= Seq(
"org.scala-lang" % "scala-reflect" % scalaVersion.value,
"org.json4s" %% "json4s-jackson" % "3.6.6",
"org.scalatest" %% "scalatest" % "3.2.0" % "test"
)
)
lazy val root = (project in file(".")) lazy val root = (project in file("."))
.dependsOn(rocketchip) .dependsOn(rocketchip)
.dependsOn(blocks)
.settings( .settings(
name := "%NAME%", name := "%NAME%",
libraryDependencies ++= Seq( libraryDependencies ++= Seq(

2
rocket-chip-blocks

Submodule rocket-chip-blocks updated: 07fd147069...42fa33b0a3

2
src/main/resources/picorv32.v
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@@ -81,7 +81,7 @@ module picorv32 #(
parameter [ 0:0] REGS_INIT_ZERO = 0, parameter [ 0:0] REGS_INIT_ZERO = 0,
parameter [31:0] MASKED_IRQ = 32'h 0000_0000, parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff, parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000, parameter [31:0] PROGADDR_RESET = 32'h 8000_0000,
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010, parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
parameter [31:0] STACKADDR = 32'h ffff_ffff parameter [31:0] STACKADDR = 32'h ffff_ffff
) ( ) (

65
src/main/scala/backBoard/pico/BackSystem.scala
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@@ -4,15 +4,18 @@ import chisel3._
import chisel3.util._ import chisel3.util._
import org.chipsalliance.cde.config._ import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import sifive.blocks.devices.uart._
import sifive.blocks.devices.gpio._
abstract class BackModule(implicit val p: Parameters) extends Module with HasBackParameters { def io: Record } abstract class BackModule(implicit val p: Parameters) extends Module with HasBackParameters { def io: Record }
abstract class BackBundle(implicit val p: Parameters) extends Bundle with HasBackParameters abstract class BackBundle(implicit val p: Parameters) extends Bundle with HasBackParameters
case object BackParamsKey extends Field[BackSetting] case object BackParamsKey extends Field[BackSetting]
case class BackSetting( case class BackSetting(
){ ){
@@ -26,7 +29,9 @@ trait HasBackParameters {
class BackCfg extends Config((_, _, _) => {
case BackParamsKey => BackSetting()
})
@@ -60,35 +65,32 @@ class BackSys()(implicit p: Parameters) extends LazyModule with HasBackParameter
beatBytes = 32/8))) beatBytes = 32/8)))
val sram = LazyModule(new TLRAM( val sram = LazyModule(new TLRAM(
address = Seq(AddressSet(0x80000000L, 0xffffL)), address = AddressSet(0x80000000L, 0xffffL),
cacheable = false, cacheable = false,
executable = true, executable = true,
atomics = false, atomics = false,
beatBytes = 4, beatBytes = 4,
ecc = ECCParams(),
sramReg = false, // drive SRAM data output directly into a register => 1 cycle longer response sramReg = false, // drive SRAM data output directly into a register => 1 cycle longer response
)) ))
val uart = LazyModule( new TLUART( // val uart = LazyModule( new TLUART(
busWidthBytes = 4, // busWidthBytes = 4,
c = UARTParams( // params = UARTParams(
address = BigInt(0x50000000L), // address = BigInt(0x50000000L),
initBaudRate = BigInt(115200), // initBaudRate = BigInt(115200),
divinit = 0 // ), divinit = 0) )
)) )
val gpio = LazyModule(new TLGPIO(busWidthBytes = 4, c = GPIOParams( // val gpio = LazyModule(new TLGPIO(busWidthBytes = 4, params = GPIOParams(
address = BigInt(0x60000000L), // address = BigInt(0x60000000L),
width = 16, // width = 16,
))) // )))
val xbar = TLXbar() val xbar = TLXbar()
xbar := coreClientNode xbar := coreClientNode
cdrNode := xbar cdrNode := xbar
sram := xbar sram.node := xbar
uart := xbar
gpio := xbar
@@ -96,8 +98,8 @@ class BackSys()(implicit p: Parameters) extends LazyModule with HasBackParameter
lazy val module: BackSysImp = new BackSysImp(this) lazy val module: BackSysImp = new BackSysImp(this)
} }
class BackSysImp(outer: BackSubSys) extends LazyModuleImp(outer) with HasBackParameters { class BackSysImp(outer: BackSys) extends LazyModuleImp(outer) with HasBackParameters {
class BackSubSysIO extends Bundle{ class BackSysIO extends Bundle{
val overCLK = Input(Bool()) val overCLK = Input(Bool())
val uDatIn = Input(Bool()) val uDatIn = Input(Bool())
val uDatOut = Output(Bool()) val uDatOut = Output(Bool())
@@ -109,7 +111,7 @@ class BackSysImp(outer: BackSubSys) extends LazyModuleImp(outer) with HasBackPar
val ( cdr_bus, cdr_edge ) = outer.cdrNode.in.head val ( cdr_bus, cdr_edge ) = outer.cdrNode.in.head
val io: BackSubSysIO = IO(new BackSubSysIO) val io: BackSysIO = IO(new BackSysIO)
val pico = Module(new Picorv32_tl(edge = core_edge)) val pico = Module(new Picorv32_tl(edge = core_edge))
val cdr = for( i <- 0 until 2 ) yield { Module(new TLCDR(cdr_edge)) } val cdr = for( i <- 0 until 2 ) yield { Module(new TLCDR(cdr_edge)) }
@@ -127,9 +129,9 @@ class BackSysImp(outer: BackSubSys) extends LazyModuleImp(outer) with HasBackPar
cdr(1).io.overCLK := io.overCLK cdr(1).io.overCLK := io.overCLK
cdr(0).io.datIn := io.uDatIn cdr(0).io.datIn := io.uDatIn
io.uDatOut := cdr(0).io.uDatOut io.uDatOut := cdr(0).io.datOut
cdr(1).io.datIn := io.dDatIn cdr(1).io.datIn := io.dDatIn
io.dDatOut := cdr(1).io.uDatOut io.dDatOut := cdr(1).io.datOut
pico.io.tld.bits := core_bus.d.bits pico.io.tld.bits := core_bus.d.bits
@@ -142,17 +144,18 @@ class BackSysImp(outer: BackSubSys) extends LazyModuleImp(outer) with HasBackPar
cdr(0).io.tla.valid := cdr_bus.a.valid & cdr_bus.a.address(7) === "h0".U cdr(0).io.tla.valid := cdr_bus.a.valid & cdr_bus.a.bits.address(7) === "h0".U
cdr(1).io.tla.valid := cdr_bus.a.valid & cdr_bus.a.address(7) === "h1".U cdr(1).io.tla.valid := cdr_bus.a.valid & cdr_bus.a.bits.address(7) === "h1".U
cdr(0).io.tla.bits := cdr_bus.a.bits cdr(0).io.tla.bits := cdr_bus.a.bits
cdr(1).io.tla.bits := cdr_bus.a.bits
cdr_bus.a.ready := cdr_bus.a.ready :=
(cdr_bus.a.address(7) === "h0".U & cdr(0).io.tla.ready) | (cdr_bus.a.bits.address(7) === "h0".U & cdr(0).io.tla.ready) |
(cdr_bus.a.address(7) === "h1".U & cdr(1).io.tla.ready) (cdr_bus.a.bits.address(7) === "h1".U & cdr(1).io.tla.ready)
cdr_bus.d.valid := cdr(0).io.tld.valid | cdr(1).io.tld.valid cdr_bus.d.valid := cdr(0).io.tld.valid | cdr(1).io.tld.valid
cdr_bus.d.bits := Mux1H(Seq( cdr_bus.d.bits := Mux1H(Seq(
cdr(0).io.tld.valid -> cdr(0).io.tld.bits cdr(0).io.tld.valid -> cdr(0).io.tld.bits,
cdr(1).io.tld.valid -> cdr(1).io.tld.bits cdr(1).io.tld.valid -> cdr(1).io.tld.bits,
)) ))
assert( ~(cdr(0).io.tld.valid & cdr(1).io.tld.valid), "Assert Failed! Two CDR can never resp at the same cycle!" ) assert( ~(cdr(0).io.tld.valid & cdr(1).io.tld.valid), "Assert Failed! Two CDR can never resp at the same cycle!" )

15
src/main/scala/backBoard/pico/Picorv32_tl.scala
View File

@@ -3,10 +3,12 @@ package BACK
import chisel3._ import chisel3._
import chisel3.util._ import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
class Picorv32_tl(edge: TLEdgeOut)(implicit p: Parameters) extends BackModule{ class Picorv32_tl(edge: TLEdgeOut)(implicit p: Parameters) extends BackModule{
val io = IO(new Bundle { class Picorv32IO_tl extends Bundle{
val trap = Output(Bool()) val trap = Output(Bool())
val tla = new DecoupledIO(new TLBundleA(edge.bundle)) val tla = new DecoupledIO(new TLBundleA(edge.bundle))
@@ -14,11 +16,11 @@ class Picorv32_tl(edge: TLEdgeOut)(implicit p: Parameters) extends BackModule {
val irq = Input(UInt(32.W)) val irq = Input(UInt(32.W))
val eoi = Output(UInt(32.W)) val eoi = Output(UInt(32.W))
}
}) val io: Picorv32IO_tl = IO(new Picorv32IO_tl)
val core = Module(new picorv32)
val core = Module(new Picorv32)
core.io.clk := clock.asBool core.io.clk := clock.asBool
core.io.resetn := ~reset.asBool core.io.resetn := ~reset.asBool
@@ -43,7 +45,7 @@ class Picorv32_tl(edge: TLEdgeOut)(implicit p: Parameters) extends BackModule {
val tlaValid = RegInit(false.B) val tlaValid = RegInit(false.B)
when( io.tlaClient.fire ){ when( io.tla.fire ){
tlaValid := false.B tlaValid := false.B
} .elsewhen( tlStateCurr === 0.U & tlStateNext === 1.U ){ } .elsewhen( tlStateCurr === 0.U & tlStateNext === 1.U ){
tlaValid := true.B tlaValid := true.B
@@ -52,6 +54,7 @@ class Picorv32_tl(edge: TLEdgeOut)(implicit p: Parameters) extends BackModule {
core.io.mem_ready := io.tld.fire core.io.mem_ready := io.tld.fire
core.io.mem_rdata := io.tld.bits.data core.io.mem_rdata := io.tld.bits.data
io.tld.ready := true.B io.tld.ready := true.B
io.tla.valid := tlaValid
when( core.io.mem_wstrb.orR ){ when( core.io.mem_wstrb.orR ){
io.tla.bits := io.tla.bits :=

41
src/main/scala/backBoard/pico/TLCDR.scala
View File

@@ -4,7 +4,8 @@ import chisel3._
import chisel3.util._ import chisel3.util._
import org.chipsalliance.cde.config._ import org.chipsalliance.cde.config._
import freechips.rocketchip.amba.axi4._ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
abstract class TLCDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends BackModule { abstract class TLCDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends BackModule {
@@ -18,14 +19,14 @@ abstract class TLCDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends Bac
val tld = new DecoupledIO(new TLBundleD(edge.bundle)) val tld = new DecoupledIO(new TLBundleD(edge.bundle))
} }
val io: TLCDRIO: IO(new TLCDRIO) val io: TLCDRIO = IO(new TLCDRIO)
val CDRIn = Module(new CDRIn) val CDRIn = Module(new CDRIn)
CDRIn.io.serDat := io.datIn CDRIn.io.serDat := io.datIn
CDRIn.io.overCLK := io.overCLK CDRIn.io.overCLK := io.overCLK
val CDROut = Module(new CDROut) val CDROut = Module(new CDROut)
io.datOut := CDROut.io serDat io.datOut := CDROut.io.serDat
// CDRIn.io.axis = Decoupled(new AXIS_Bundle(8)) // CDRIn.io.axis = Decoupled(new AXIS_Bundle(8))
@@ -40,9 +41,9 @@ abstract class TLCDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends Bac
trait TLCDRTx{ this: TLCDRBase => trait TLCDRTx{ this: TLCDRBase =>
val isTLReadTxStatus = io.tla.fire & io.tla.bits.address(7,0) === "h0".U & ( io.tla.bits.opcode === 4.U ) val isTLReadTxStatus = io.tla.fire & io.tla.bits.address(6,0) === "h0".U & ( io.tla.bits.opcode === 4.U )
val isTLWriteTxLen = io.tla.fire & io.tla.bits.address(7,0) === "h4".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) val isTLWriteTxLen = io.tla.fire & io.tla.bits.address(6,0) === "h4".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val isTLWriteTxFifo = io.tla.fire & io.tla.bits.address(7,0) === "h8".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) val isTLWriteTxFifo = io.tla.fire & io.tla.bits.address(6,0) === "h8".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val isTLWriteTxSoftReset = isTLWriteTxLen val isTLWriteTxSoftReset = isTLWriteTxLen
@@ -72,7 +73,7 @@ trait TLCDRTx{ this: TLCDRBase =>
CDROut.io.axis.bits.tlast := txLen === 0.U & ~txFifo.io.deq.valid & txCnt === 3.U CDROut.io.axis.bits.tlast := txLen === 0.U & ~txFifo.io.deq.valid & txCnt === 3.U
CDROut.io.axis.bits.tuser := isTxError CDROut.io.axis.bits.tuser := isTxError
CDROut.io.axis.bits.valid := isTxBusy CDROut.io.axis.valid := isTxBusy
when( isTLWriteTxLen ){ when( isTLWriteTxLen ){
@@ -115,10 +116,10 @@ trait TLCDRTx{ this: TLCDRBase =>
trait TLCDRRx{ this: TLCDRBase => trait TLCDRRx{ this: TLCDRBase =>
val isTLWriteRxSoftReset = io.tla.fire & io.tla.bits.address(7,0) === "h10".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) val isTLWriteRxSoftReset = io.tla.fire & io.tla.bits.address(6,0) === "h10".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val isTLReadRxStatus = io.tla.fire & io.tla.bits.address(7,0) === "h14".U & ( io.tla.bits.opcode === 4.U ) val isTLReadRxStatus = io.tla.fire & io.tla.bits.address(6,0) === "h14".U & ( io.tla.bits.opcode === 4.U )
val isTLReadRxLen = io.tla.fire & io.tla.bits.address(7,0) === "h18".U & ( io.tla.bits.opcode === 4.U ) val isTLReadRxLen = io.tla.fire & io.tla.bits.address(6,0) === "h18".U & ( io.tla.bits.opcode === 4.U )
val isTLReadRxFifo = io.tla.fire & io.tla.bits.address(7,0) === "h1c".U & ( io.tla.bits.opcode === 4.U ) val isTLReadRxFifo = io.tla.fire & io.tla.bits.address(6,0) === "h1c".U & ( io.tla.bits.opcode === 4.U )
val rxLen = RegInit(0.U(32.W)) val rxLen = RegInit(0.U(32.W))
// val isRxBusy = RegInit(false.B) // val isRxBusy = RegInit(false.B)
@@ -139,10 +140,10 @@ trait TLCDRRx{ this: TLCDRBase =>
rxCnt := rxCnt + 1.U rxCnt := rxCnt + 1.U
rxData := Mux1H(Seq( rxData := Mux1H(Seq(
(rxCnt === 0.U) -> Cat( 0.U(24.W), CDRIn.io.axis.bits.tdata ) (rxCnt === 0.U) -> Cat( 0.U(24.W), CDRIn.io.axis.bits.tdata ),
(rxCnt === 1.U) -> Cat( 0.U(16.W), CDRIn.io.axis.bits.tdata, rxData( 7,0) ) (rxCnt === 1.U) -> Cat( 0.U(16.W), CDRIn.io.axis.bits.tdata, rxData( 7,0) ),
(rxCnt === 2.U) -> Cat( 0.U(8.W ), CDRIn.io.axis.bits.tdata, rxData(15,0) ) (rxCnt === 2.U) -> Cat( 0.U(8.W ), CDRIn.io.axis.bits.tdata, rxData(15,0) ),
// (rxCnt === 3.U) -> Cat( CDRIn.io.axis.bits.tdata, rxData(23,0) ) // (rxCnt === 3.U) -> Cat( CDRIn.io.axis.bits.tdata, rxData(23,0) ),
)) ))
} }
@@ -152,12 +153,12 @@ trait TLCDRRx{ this: TLCDRBase =>
rxLen := rxLen + 1.U rxLen := rxLen + 1.U
} }
rxFifo.io.enq.valid := CDRIn.io.axis.fire & ( rxCnt === 3.U | CDRIn.io.axis.bits.last ) rxFifo.io.enq.valid := CDRIn.io.axis.fire & ( rxCnt === 3.U | CDRIn.io.axis.bits.tlast )
rxFifo.io.enq.bits := Mux1H(Seq( rxFifo.io.enq.bits := Mux1H(Seq(
(rxCnt === 0.U) -> Cat( 0.U(24.W), CDRIn.io.axis.bits.tdata ) (rxCnt === 0.U) -> Cat( 0.U(24.W), CDRIn.io.axis.bits.tdata ),
(rxCnt === 1.U) -> Cat( 0.U(16.W), CDRIn.io.axis.bits.tdata, rxData( 7,0) ) (rxCnt === 1.U) -> Cat( 0.U(16.W), CDRIn.io.axis.bits.tdata, rxData( 7,0) ),
(rxCnt === 2.U) -> Cat( 0.U(8.W ), CDRIn.io.axis.bits.tdata, rxData(15,0) ) (rxCnt === 2.U) -> Cat( 0.U(8.W ), CDRIn.io.axis.bits.tdata, rxData(15,0) ),
(rxCnt === 3.U) -> Cat( CDRIn.io.axis.bits.tdata, rxData(23,0) ) (rxCnt === 3.U) -> Cat( CDRIn.io.axis.bits.tdata, rxData(23,0) ),
)) ))
CDRIn.io.axis.ready := true.B CDRIn.io.axis.ready := true.B

2
src/main/scala/backBoard/pico/picorv32.scala
View File

@@ -7,7 +7,7 @@ import chisel3.experimental._
class Picorv32 extends BlackBox() with HasBlackBoxResource { class picorv32 extends BlackBox() with HasBlackBoxResource {
val io = IO(new Bundle { val io = IO(new Bundle {
val clk = Input(Bool()) val clk = Input(Bool())
val resetn = Input(Bool()) val resetn = Input(Bool())

14
src/test/scala/gcd/test.scala
View File

@@ -54,8 +54,18 @@ object testModule extends App {
// ChiselGeneratorAnnotation(() => { new ShinSlvBase }) // ChiselGeneratorAnnotation(() => { new ShinSlvBase })
// )) // ))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq( // (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new picorv32_tl }) // ChiselGeneratorAnnotation(() => { new picorv32_tl })
// ))
val cfg = new BackCfg
(new chisel3.stage.ChiselStage).execute( Array("--show-registrations", "--full-stacktrace", "--target-dir", "generated/cdr/", "-e", "verilog") ++ args, Seq(
ChiselGeneratorAnnotation(() => {
val soc = LazyModule(new BackSys()(cfg))
soc.module
})
)) ))

88
tb/backSys_tb.v Normal file
View File

@@ -0,0 +1,88 @@
`timescale 1 ns / 1 ps
module backSys_TB (
);
reg clock;
reg reset;
reg overCLK;
wire io_uDatIn;
wire io_uDatOut;
wire io_dDatIn;
wire io_dDatOut;
BackSys s_BackSys(
.clock(clock),
.reset(reset),
.io_overCLK(overCLK),
.io_uDatIn(io_uDatIn),
.io_uDatOut(io_uDatOut),
.io_dDatIn(io_dDatIn),
.io_dDatOut(io_dDatOut)
);
initial begin
clock = 0;
reset = 1;
#200
reset <= 0;
#160000
$display("Time Out !!!");
$stop;
end
initial begin
forever begin #40 clock <= ~clock; end
end
initial begin
forever begin #10 overCLK <= ~overCLK; end
end
`define SRAM0 s_BackSys.sram.mem_0
`define SRAM1 s_BackSys.sram.mem_1
`define SRAM2 s_BackSys.sram.mem_2
`define SRAM3 s_BackSys.sram.mem_3
localparam DP = 2**14;
integer i, by;
reg [7:0] mem [0:200000];
initial begin
$readmemh("./tb/sw/build/test.verilog", mem);
for ( i = 0; i < DP; i = i + 1 ) begin
`SRAM0[i] = | mem[i*4+0] ? mem[i*4+0]: 8'h0;
`SRAM1[i] = | mem[i*4+1] ? mem[i*4+1]: 8'h0;
`SRAM2[i] = | mem[i*4+2] ? mem[i*4+2]: 8'h0;
`SRAM3[i] = | mem[i*4+3] ? mem[i*4+3]: 8'h0;
// $display("ITCM %h: %h,%h", i*4,`SRAM_ODD.ram[i],`SRAM_EVE.ram[i]);
end
end
initial
begin
$dumpfile("./build/wave.vcd"); //生成的vcd文件名称
$dumpvars(0, backSys_TB);//tb模块名称
end
endmodule

5
tb/sw/.gitignore vendored Normal file
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*.elf
*.o
*.img
*.bin

40
tb/sw/axi_gpio/gpio.c Normal file
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#include <stdint.h>
#include "gpio.h"
#ifndef GPIO_BASE
#error GPIO Base address not define!!!
#endif
// for 8 bit gpio
volatile uint32_t *gpio_dat_reg = (uint32_t*)( GPIO_BASE + GPIO_DATA );
volatile uint32_t *gpio_tri_reg = (uint32_t*)( GPIO_BASE + GPIO_TRI );
uint8_t gpio_read()
{
*gpio_tri_reg = 0xff;
return (uint8_t)(*gpio_dat_reg);
}
uint32_t gpio_write( uint32_t data )
{
*gpio_tri_reg = 0x00;
(*gpio_dat_reg) = data;
return 0;
}

24
tb/sw/axi_gpio/gpio.h Normal file
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#ifndef _GPIO_H_
#define _GPIO_H_
#include <stdint.h>
#define GPIO_BASE 0x20000000U
#define GPIO_DATA 0x0000
#define GPIO_TRI 0x0004
#define GPIO2_DATA 0x0008
#define GPIO2_TRI 0x000C
#define GIER 0x011C
#define IP_IER 0x0128
#define IP_ISR 0x0120
extern uint8_t gpio_read();
extern uint32_t gpio_write( uint32_t data );
void gpio_test();
#endif

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/*
* @Author: Ruige Lee
* @Date: 2020-10-12 14:27:54
* @Last Modified by: Ruige Lee
* @Last Modified time: 2020-10-12 17:16:04
*/
#include <stdint.h>
#include "timer.h"
#ifndef TIMER_BASE
#error Timer Base address not define!!!
#endif
volatile uint32_t *timer_tcsr0_reg = (uint32_t*)( TIMER_BASE + TIMER_TCSR0 );
volatile uint32_t *timer_tlr0_reg = (uint32_t*)( TIMER_BASE + TIMER_TLR0 );
volatile uint32_t *timer_tcr0_reg = (uint32_t*)( TIMER_BASE + TIMER_TCR0 );
volatile uint32_t *timer_tcsr1_reg = (uint32_t*)( TIMER_BASE + TIMER_TCSR1 );
volatile uint32_t *timer_tlr1_reg = (uint32_t*)( TIMER_BASE + TIMER_TLR1 );
volatile uint32_t *timer_tcr1_reg = (uint32_t*)( TIMER_BASE + TIMER_TCR1 );
int32_t timerIsINT(uint8_t timerNo)
{
if ( ( ( (*timer_tcsr0_reg) & 0x00000100 ) && ( timerNo == 0 ) )
||
( ( (*timer_tcsr1_reg) & 0x00000100 ) && ( timerNo == 1 ) )
)
{
return 1;
}
else
{
return 0;
}
}
int32_t timerClearINT(uint8_t timerNo)
{
if ( timerNo == 0 )
{
*timer_tcsr0_reg = (*timer_tcsr0_reg) | 0x00000100;
}
else
{
*timer_tcsr1_reg = (*timer_tcsr1_reg) | 0x00000100;
}
return 0;
}
int32_t timerEnableRun(uint8_t timerNo)
{
if ( timerNo == 0 )
{
*timer_tcsr0_reg = (*timer_tcsr0_reg) | 0x00000080;
}
else
{
*timer_tcsr1_reg = (*timer_tcsr1_reg) | 0x00000080;
}
return 0;
}
int32_t timerDisableRun(uint8_t timerNo)
{
if ( timerNo == 0 )
{
*timer_tcsr0_reg = (*timer_tcsr0_reg) & (~0x00000080);
}
else
{
*timer_tcsr1_reg = (*timer_tcsr1_reg) & (~0x00000080);
}
return 0;
}
int32_t timerEnableINT(uint8_t timerNo)
{
if ( timerNo == 0 )
{
*timer_tcsr0_reg = (*timer_tcsr0_reg) & (~0x00000020);
*timer_tcsr0_reg = (*timer_tcsr0_reg) | 0x00000040;
}
else
{
*timer_tcsr1_reg = (*timer_tcsr1_reg) & (~0x00000020);
*timer_tcsr1_reg = (*timer_tcsr1_reg) | 0x00000040;
}
return 0;
}
int32_t timerDisableINT(uint8_t timerNo)
{
if ( timerNo == 0 )
{
*timer_tcsr0_reg = (*timer_tcsr0_reg) & (~0x00000040);
}
else
{
*timer_tcsr1_reg = (*timer_tcsr1_reg) & (~0x00000040);
}
return 0;
}
int32_t timerLoad(uint8_t timerNo, uint32_t count)
{
if ( timerNo == 0 )
{
*timer_tlr0_reg = count;
*timer_tcsr0_reg = (*timer_tcsr0_reg) | 0x00000020;
}
else
{
*timer_tlr1_reg = count;
*timer_tcsr1_reg = (*timer_tcsr1_reg) | 0x00000020;
}
return 0;
}
int32_t timerAutoReloadEnable(uint8_t timerNo)
{
if ( timerNo == 0 )
{
*timer_tcsr0_reg = (*timer_tcsr0_reg) | 0x00000010;
}
else
{
*timer_tcsr1_reg = (*timer_tcsr1_reg) | 0x00000010;
}
return 0;
}
int32_t timerAutoReloadDisable(uint8_t timerNo)
{
if ( timerNo == 0 )
{
*timer_tcsr0_reg = (*timer_tcsr0_reg) & (~0x00000010);
}
else
{
*timer_tcsr1_reg = (*timer_tcsr1_reg) & (~0x00000010);
}
return 0;
}
int32_t timerUpCount(uint8_t timerNo)
{
if ( timerNo == 0 )
{
*timer_tcsr0_reg = (*timer_tcsr0_reg) & (~0x00000002);
}
else
{
*timer_tcsr1_reg = (*timer_tcsr1_reg) & (~0x00000002);
}
return 0;
}
int32_t timerDownCount(uint8_t timerNo)
{
if ( timerNo == 0 )
{
*timer_tcsr0_reg = (*timer_tcsr0_reg) | 0x00000002;
}
else
{
*timer_tcsr1_reg = (*timer_tcsr1_reg) | 0x00000002;
}
return 0;
}
int32_t timerGenerate(uint8_t timerNo)
{
if ( timerNo == 0 )
{
*timer_tcsr0_reg = (*timer_tcsr0_reg) & (~0x00000001);
}
else
{
*timer_tcsr1_reg = (*timer_tcsr1_reg) & (~0x00000001);
}
return 0;
}
int32_t timerCapture( uint8_t timerNo )
{
if ( timerNo == 0 )
{
*timer_tcsr0_reg = (*timer_tcsr0_reg) | 0x00000001;
}
else
{
*timer_tcsr1_reg = (*timer_tcsr1_reg) | 0x00000001;
}
return 0;
}
uint32_t timerCounterRead( uint8_t timerNo )
{
if ( timerNo == 0 )
{
return *timer_tcr0_reg;
}
else
{
return *timer_tcr1_reg;
}
}

50
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#ifndef _TIMER_H_
#define _TIMER_H_
#include <stdint.h>
#define TIMER_BASE 0x20000800U
#define TIMER_TCSR0 0x00U
#define TIMER_TLR0 0x04
#define TIMER_TCR0 0x08
// #define TIMER_RSVD
#define TIMER_TCSR1 0x10U
#define TIMER_TLR1 0x14U
#define TIMER_TCR1 0x18U
extern int32_t timerIsINT( uint8_t timerNo );
extern int32_t timerClearINT( uint8_t timerNo );
extern int32_t timerEnableRun( uint8_t timerNo );
extern int32_t timerDisableRun( uint8_t timerNo );
extern int32_t timerEnableINT( uint8_t timerNo );
extern int32_t timerDisableINT( uint8_t timerNo );
extern int32_t timerLoad( uint8_t timerNo, uint32_t count );
extern int32_t timerAutoReloadEnable( uint8_t timerNo );
extern int32_t timerAutoReloadDisable( uint8_t timerNo );
extern int32_t timerUpCount( uint8_t timerNo );
extern int32_t timerDownCount( uint8_t timerNo );
extern int32_t timerGenerate( uint8_t timerNo );
extern int32_t timerCapture( uint8_t timerNo );
extern uint32_t timerCounterRead( uint8_t timerNo );
#endif

78
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#include <stdint.h>
#include "uart.h"
#ifndef UART_BASE
#error UART Base address not define!!!
#endif
volatile uint32_t *uart_rfifo = (uint32_t*)( UART_BASE + RX_FIFO );
volatile uint32_t *uart_tfifo = (uint32_t*)( UART_BASE + TX_FIFO );
volatile uint32_t *uart_status = (uint32_t*)( UART_BASE + STAT_REG );
volatile uint32_t *uart_ctrl = (uint32_t*)( UART_BASE + CTRL_REG );
int32_t uart_init()
{
//reset rx & tx fifo, disable interrupt
(*uart_status) = 0x03;
(*uart_status) = 0x00;
return 0;
}
int32_t uart_sendByte( uint8_t data )
{
#if(1)
//wait unitl tx fifo not full
while( ((*uart_status) & 0x08) != 0);
*uart_tfifo = data;
#else
(*(volatile uint32_t*)(0x60000000)) = data;
#endif
return 0;
}
uint8_t uart_recByte()
{
//wait unitl rx fifo has data
while( ((*uart_status) & 0x01) == 0);
return (uint8_t)(*uart_rfifo);
}
int32_t print_uart(const char *str)
{
const char *cur = &str[0];
while (*cur != '\0')
{
uart_sendByte((uint8_t)*cur);
cur++;
}
return 0;
}

26
tb/sw/axi_uart/uart.h Normal file
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#ifndef _UART_H_
#define _UART_H_
#include <stdint.h>
#define UART_BASE 0x60000000U
#define RX_FIFO 0x0000
#define TX_FIFO 0x0004
#define STAT_REG 0x0008
#define CTRL_REG 0x000c
extern int32_t uart_init();
extern int32_t uart_sendByte( uint8_t data );
extern uint8_t uart_recByte();
extern int32_t print_uart(const char *str);
#endif

39
tb/sw/linker.lds Normal file
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ENTRY(_prog_start)
SECTIONS
{
RAM_BASE = 0x80000000;
. = RAM_BASE;
.text.init : { *(.text.init) }
.text : ALIGN(0x100) {
_TEXT_START_ = .;
*(.text)
_TEXT_END_ = .;
}
.data : ALIGN(0x100) {
_DATA_START_ = .;
*(.data)
_DATA_END_ = .;
}
PROVIDE(_data = ADDR(.data));
PROVIDE(_data_lma = LOADADDR(.data));
PROVIDE(_edata = .);
.bss : ALIGN(0x100) {
_BSS_START_ = .;
*(.bss)
_BSS_END_ = .;
}
.rodata : ALIGN(0x100) {
_RODATA_START_ = .;
*(.rodata)
*(.rodata*)
_RODATA_END_ = .;
}
}

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tb/sw/src/main.c Normal file
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#include <stdint.h>
// #include "uart.h"
// #include "gpio.h"
// #include "timer.h"
volatile uint32_t *cdr_0_tx_status = (uint32_t*)( 0x40000000 + 0x0 ); //read
volatile uint32_t *cdr_0_tx_txLen = (uint32_t*)( 0x40000000 + 0x4 ); //write
volatile uint32_t *cdr_0_tx_txFifo = (uint32_t*)( 0x40000000 + 0x8 ); //write
volatile uint32_t *cdr_0_rx_softReset = (uint32_t*)( 0x40000000 + 0x10 ); //write
volatile uint32_t *cdr_0_rx_status = (uint32_t*)( 0x40000000 + 0x14 ); //read
volatile uint32_t *cdr_0_rx_rxLen = (uint32_t*)( 0x40000000 + 0x18 ); //read
volatile uint32_t *cdr_0_rx_rxFifo = (uint32_t*)( 0x40000000 + 0x1c ); //read
volatile uint32_t *cdr_1_tx_status = (uint32_t*)( 0x40000080 + 0x0 ); //read
volatile uint32_t *cdr_1_tx_txLen = (uint32_t*)( 0x40000080 + 0x4 ); //write
volatile uint32_t *cdr_1_tx_txFifo = (uint32_t*)( 0x40000080 + 0x8 ); //write
volatile uint32_t *cdr_1_rx_softReset = (uint32_t*)( 0x40000080 + 0x10 ); //write
volatile uint32_t *cdr_1_rx_status = (uint32_t*)( 0x40000080 + 0x14 ); //read
volatile uint32_t *cdr_1_rx_rxLen = (uint32_t*)( 0x40000080 + 0x18 ); //read
volatile uint32_t *cdr_1_rx_rxFifo = (uint32_t*)( 0x40000080 + 0x1c ); //read
int main()
{
// uart_init();
// print_uart("Hello World, RocketChip is now Waking Up!\r\n");
// gpio_write( 0xfffffffa );
// for ( i = 0; i < 255; i++ )
// {
// *(txBuf+i) = data;
// data = data << 4 | data >> 60;
// }
// udelay(50);
*(cdr_0_tx_txLen) = 32;
for( uint8_t i = 0; i < 32; i ++ ){
*cdr_0_tx_txFifo = 32-i;
}
while(1)
{
;
}
return 0;
}
void handle_trap(void)
{
}

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.section .text.init
.globl _prog_start
_prog_start:
li x1, 0
li x2, 0
li x3, 0
li x4, 0
li x5, 0
li x6, 0
li x7, 0
li x8, 0
li x9, 0
li x10,0
li x11,0
li x12,0
li x13,0
li x14,0
li x15,0
li x16,0
li x17,0
li x18,0
li x19,0
li x20,0
li x21,0
li x22,0
li x23,0
li x24,0
li x25,0
li x26,0
li x27,0
li x28,0
li x29,0
li x30,0
li x31,0
# li t0, 0xffff
# csrc mie, t0
# li t0, 0xa
# csrc mstatus, t0
li sp, 0x80010000
# la t0, trap_entry
# csrw mtvec, t0
call main
li gp, 1;
ecall
trap_entry:
addi sp, sp, -136
sw x1, 1* 4(sp)
sw x2, 2* 4(sp)
sw x3, 3* 4(sp)
sw x4, 4* 4(sp)
sw x5, 5* 4(sp)
sw x6, 6* 4(sp)
sw x7, 7* 4(sp)
sw x8, 8* 4(sp)
sw x9, 9* 4(sp)
sw x10, 10*4(sp)
sw x11, 11*4(sp)
sw x12, 12*4(sp)
sw x13, 13*4(sp)
sw x14, 14*4(sp)
sw x15, 15*4(sp)
sw x16, 16*4(sp)
sw x17, 17*4(sp)
sw x18, 18*4(sp)
sw x19, 19*4(sp)
sw x20, 20*4(sp)
sw x21, 21*4(sp)
sw x22, 22*4(sp)
sw x23, 23*4(sp)
sw x24, 24*4(sp)
sw x25, 25*4(sp)
sw x26, 26*4(sp)
sw x27, 27*4(sp)
sw x28, 28*4(sp)
sw x29, 29*4(sp)
sw x30, 30*4(sp)
sw x31, 31*4(sp)
# csrr a0, mcause
# csrr a1, mepc
mv a2, sp
jal handle_trap
# csrw mepc, a0
# li t0, MSTATUS_MPP
# csrs mstatus, t0
lw x1, 1 *4(sp)
lw x2, 2 *4(sp)
lw x3, 3 *4(sp)
lw x4, 4 *4(sp)
lw x5, 5 *4(sp)
lw x6, 6 *4(sp)
lw x7, 7 *4(sp)
lw x8, 8 *4(sp)
lw x9, 9 *4(sp)
lw x10, 10*4(sp)
lw x11, 11*4(sp)
lw x12, 12*4(sp)
lw x13, 13*4(sp)
lw x14, 14*4(sp)
lw x15, 15*4(sp)
lw x16, 16*4(sp)
lw x17, 17*4(sp)
lw x18, 18*4(sp)
lw x19, 19*4(sp)
lw x20, 20*4(sp)
lw x21, 21*4(sp)
lw x22, 22*4(sp)
lw x23, 23*4(sp)
lw x24, 24*4(sp)
lw x25, 25*4(sp)
lw x26, 26*4(sp)
lw x27, 27*4(sp)
lw x28, 28*4(sp)
lw x29, 29*4(sp)
lw x30, 30*4(sp)
lw x31, 31*4(sp)
addi sp, sp, 136
mret