编译通过 仿真启动 请知悉 改处理器没有csr
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RuigeLee
64
tb/sw/src/main.c
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64
tb/sw/src/main.c
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#include <stdint.h>
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// #include "uart.h"
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// #include "gpio.h"
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// #include "timer.h"
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volatile uint32_t *cdr_0_tx_status = (uint32_t*)( 0x40000000 + 0x0 ); //read
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volatile uint32_t *cdr_0_tx_txLen = (uint32_t*)( 0x40000000 + 0x4 ); //write
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volatile uint32_t *cdr_0_tx_txFifo = (uint32_t*)( 0x40000000 + 0x8 ); //write
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volatile uint32_t *cdr_0_rx_softReset = (uint32_t*)( 0x40000000 + 0x10 ); //write
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volatile uint32_t *cdr_0_rx_status = (uint32_t*)( 0x40000000 + 0x14 ); //read
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volatile uint32_t *cdr_0_rx_rxLen = (uint32_t*)( 0x40000000 + 0x18 ); //read
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volatile uint32_t *cdr_0_rx_rxFifo = (uint32_t*)( 0x40000000 + 0x1c ); //read
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volatile uint32_t *cdr_1_tx_status = (uint32_t*)( 0x40000080 + 0x0 ); //read
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volatile uint32_t *cdr_1_tx_txLen = (uint32_t*)( 0x40000080 + 0x4 ); //write
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volatile uint32_t *cdr_1_tx_txFifo = (uint32_t*)( 0x40000080 + 0x8 ); //write
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volatile uint32_t *cdr_1_rx_softReset = (uint32_t*)( 0x40000080 + 0x10 ); //write
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volatile uint32_t *cdr_1_rx_status = (uint32_t*)( 0x40000080 + 0x14 ); //read
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volatile uint32_t *cdr_1_rx_rxLen = (uint32_t*)( 0x40000080 + 0x18 ); //read
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volatile uint32_t *cdr_1_rx_rxFifo = (uint32_t*)( 0x40000080 + 0x1c ); //read
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int main()
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{
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// uart_init();
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// print_uart("Hello World, RocketChip is now Waking Up!\r\n");
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// gpio_write( 0xfffffffa );
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// for ( i = 0; i < 255; i++ )
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// {
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// *(txBuf+i) = data;
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// data = data << 4 | data >> 60;
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// }
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// udelay(50);
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*(cdr_0_tx_txLen) = 32;
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for( uint8_t i = 0; i < 32; i ++ ){
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*cdr_0_tx_txFifo = 32-i;
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}
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while(1)
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{
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;
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}
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return 0;
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}
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void handle_trap(void)
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{
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}
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134
tb/sw/src/startup.S
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134
tb/sw/src/startup.S
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.section .text.init
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.globl _prog_start
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_prog_start:
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li x1, 0
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li x2, 0
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li x3, 0
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li x4, 0
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li x5, 0
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li x6, 0
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li x7, 0
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li x8, 0
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li x9, 0
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li x10,0
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li x11,0
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li x12,0
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li x13,0
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li x14,0
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li x15,0
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li x16,0
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li x17,0
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li x18,0
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li x19,0
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li x20,0
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li x21,0
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li x22,0
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li x23,0
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li x24,0
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li x25,0
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li x26,0
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li x27,0
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li x28,0
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li x29,0
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li x30,0
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li x31,0
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# li t0, 0xffff
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# csrc mie, t0
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# li t0, 0xa
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# csrc mstatus, t0
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li sp, 0x80010000
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# la t0, trap_entry
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# csrw mtvec, t0
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call main
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li gp, 1;
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ecall
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trap_entry:
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addi sp, sp, -136
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sw x1, 1* 4(sp)
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sw x2, 2* 4(sp)
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sw x3, 3* 4(sp)
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sw x4, 4* 4(sp)
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sw x5, 5* 4(sp)
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sw x6, 6* 4(sp)
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sw x7, 7* 4(sp)
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sw x8, 8* 4(sp)
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sw x9, 9* 4(sp)
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sw x10, 10*4(sp)
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sw x11, 11*4(sp)
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sw x12, 12*4(sp)
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sw x13, 13*4(sp)
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sw x14, 14*4(sp)
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sw x15, 15*4(sp)
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sw x16, 16*4(sp)
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sw x17, 17*4(sp)
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sw x18, 18*4(sp)
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sw x19, 19*4(sp)
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sw x20, 20*4(sp)
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sw x21, 21*4(sp)
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sw x22, 22*4(sp)
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sw x23, 23*4(sp)
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sw x24, 24*4(sp)
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sw x25, 25*4(sp)
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sw x26, 26*4(sp)
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sw x27, 27*4(sp)
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sw x28, 28*4(sp)
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sw x29, 29*4(sp)
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sw x30, 30*4(sp)
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sw x31, 31*4(sp)
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# csrr a0, mcause
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# csrr a1, mepc
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mv a2, sp
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jal handle_trap
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# csrw mepc, a0
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# li t0, MSTATUS_MPP
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# csrs mstatus, t0
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lw x1, 1 *4(sp)
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lw x2, 2 *4(sp)
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lw x3, 3 *4(sp)
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lw x4, 4 *4(sp)
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lw x5, 5 *4(sp)
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lw x6, 6 *4(sp)
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lw x7, 7 *4(sp)
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lw x8, 8 *4(sp)
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lw x9, 9 *4(sp)
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lw x10, 10*4(sp)
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lw x11, 11*4(sp)
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lw x12, 12*4(sp)
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lw x13, 13*4(sp)
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lw x14, 14*4(sp)
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lw x15, 15*4(sp)
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lw x16, 16*4(sp)
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lw x17, 17*4(sp)
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lw x18, 18*4(sp)
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lw x19, 19*4(sp)
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lw x20, 20*4(sp)
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lw x21, 21*4(sp)
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lw x22, 22*4(sp)
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lw x23, 23*4(sp)
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lw x24, 24*4(sp)
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lw x25, 25*4(sp)
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lw x26, 26*4(sp)
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lw x27, 27*4(sp)
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lw x28, 28*4(sp)
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lw x29, 29*4(sp)
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lw x30, 30*4(sp)
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lw x31, 31*4(sp)
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addi sp, sp, 136
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mret
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