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tb/backSys_tb.v

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+`timescale 1 ns / 1 ps
+
+
+
+module backSys_TB (
+
+);
+
+
+  reg   clock;
+  reg   reset;
+
+  reg  overCLK;
+
+  wire  io_uDatIn;
+  wire  io_uDatOut;
+  wire  io_dDatIn;
+  wire  io_dDatOut;
+
+
+BackSys s_BackSys(
+  .clock(clock),
+  .reset(reset),
+  .io_overCLK(overCLK),
+  .io_uDatIn(io_uDatIn),
+  .io_uDatOut(io_uDatOut),
+  .io_dDatIn(io_dDatIn),
+  .io_dDatOut(io_dDatOut)
+);
+
+
+
+initial begin
+	clock = 0;
+	reset = 1;
+
+	#200
+
+	reset <= 0;
+
+	#160000
+			$display("Time Out !!!");
+	$stop;
+end
+
+
+initial begin
+	forever begin #40 clock <= ~clock; end
+end
+
+initial begin
+	forever begin  #10 overCLK <= ~overCLK; end
+end
+
+
+`define SRAM0 s_BackSys.sram.mem_0
+`define SRAM1 s_BackSys.sram.mem_1
+`define SRAM2 s_BackSys.sram.mem_2
+`define SRAM3 s_BackSys.sram.mem_3
+
+
+	localparam DP = 2**14;
+	integer i, by;
+
+		reg [7:0] mem [0:200000];
+		initial begin
+			$readmemh("./tb/sw/build/test.verilog", mem);
+			for ( i = 0; i < DP; i = i + 1 ) begin
+				`SRAM0[i] = | mem[i*4+0] ? mem[i*4+0]: 8'h0;
+				`SRAM1[i] = | mem[i*4+1] ? mem[i*4+1]: 8'h0;
+				`SRAM2[i] = | mem[i*4+2] ? mem[i*4+2]: 8'h0;
+				`SRAM3[i] = | mem[i*4+3] ? mem[i*4+3]: 8'h0;
+
+				// $display("ITCM %h: %h,%h", i*4,`SRAM_ODD.ram[i],`SRAM_EVE.ram[i]);
+			end
+
+		end 
+
+
+
+initial
+begin
+	$dumpfile("./build/wave.vcd"); //生成的vcd文件名称
+	$dumpvars(0, backSys_TB);//tb模块名称
+end
+
+endmodule
+