编译通过 仿真启动 请知悉 改处理器没有csr

src/test/scala/gcd/test.scala

@@ -54,9 +54,19 @@ object testModule extends App {
   //     ChiselGeneratorAnnotation(() => { new ShinSlvBase })
   //   ))
 
-   (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
-      ChiselGeneratorAnnotation(() => { new picorv32_tl })
-    ))
+  //  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
+  //     ChiselGeneratorAnnotation(() => { new picorv32_tl })
+  //   ))
+
+
+  val cfg = new BackCfg
+
+  (new chisel3.stage.ChiselStage).execute( Array("--show-registrations", "--full-stacktrace", "--target-dir", "generated/cdr/", "-e", "verilog") ++ args, Seq(
+      ChiselGeneratorAnnotation(() => {
+    val soc = LazyModule(new BackSys()(cfg))
+    soc.module
+  })
+  ))
 
 
   // (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(