ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

编译通过 仿真启动 请知悉 改处理器没有csr

Browse Source
This commit is contained in:
RuigeLee
2024-10-25 17:46:21 +08:00
parent 4737700f56
commit 78d54d2083
20 changed files with 880 additions and 69 deletions
Download Patch File Download Diff File Expand all files Collapse all files

41
src/main/scala/backBoard/pico/TLCDR.scala
View File

@@ -4,7 +4,8 @@ import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.amba.axi4._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
abstract class TLCDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends BackModule {
@@ -18,14 +19,14 @@ abstract class TLCDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends Bac
val tld = new DecoupledIO(new TLBundleD(edge.bundle))
}
val io: TLCDRIO: IO(new TLCDRIO)
val io: TLCDRIO = IO(new TLCDRIO)
val CDRIn = Module(new CDRIn)
CDRIn.io.serDat := io.datIn
CDRIn.io.overCLK := io.overCLK
val CDROut = Module(new CDROut)
io.datOut := CDROut.io serDat
io.datOut := CDROut.io.serDat
// CDRIn.io.axis = Decoupled(new AXIS_Bundle(8))
@@ -40,9 +41,9 @@ abstract class TLCDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends Bac
trait TLCDRTx{ this: TLCDRBase =>
val isTLReadTxStatus = io.tla.fire & io.tla.bits.address(7,0) === "h0".U & ( io.tla.bits.opcode === 4.U )
val isTLWriteTxLen = io.tla.fire & io.tla.bits.address(7,0) === "h4".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val isTLWriteTxFifo = io.tla.fire & io.tla.bits.address(7,0) === "h8".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val isTLReadTxStatus = io.tla.fire & io.tla.bits.address(6,0) === "h0".U & ( io.tla.bits.opcode === 4.U )
val isTLWriteTxLen = io.tla.fire & io.tla.bits.address(6,0) === "h4".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val isTLWriteTxFifo = io.tla.fire & io.tla.bits.address(6,0) === "h8".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val isTLWriteTxSoftReset = isTLWriteTxLen
@@ -72,7 +73,7 @@ trait TLCDRTx{ this: TLCDRBase =>
CDROut.io.axis.bits.tlast := txLen === 0.U & ~txFifo.io.deq.valid & txCnt === 3.U
CDROut.io.axis.bits.tuser := isTxError
CDROut.io.axis.bits.valid := isTxBusy
CDROut.io.axis.valid := isTxBusy
when( isTLWriteTxLen ){
@@ -115,10 +116,10 @@ trait TLCDRTx{ this: TLCDRBase =>
trait TLCDRRx{ this: TLCDRBase =>
val isTLWriteRxSoftReset = io.tla.fire & io.tla.bits.address(7,0) === "h10".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val isTLReadRxStatus = io.tla.fire & io.tla.bits.address(7,0) === "h14".U & ( io.tla.bits.opcode === 4.U )
val isTLReadRxLen = io.tla.fire & io.tla.bits.address(7,0) === "h18".U & ( io.tla.bits.opcode === 4.U )
val isTLReadRxFifo = io.tla.fire & io.tla.bits.address(7,0) === "h1c".U & ( io.tla.bits.opcode === 4.U )
val isTLWriteRxSoftReset = io.tla.fire & io.tla.bits.address(6,0) === "h10".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val isTLReadRxStatus = io.tla.fire & io.tla.bits.address(6,0) === "h14".U & ( io.tla.bits.opcode === 4.U )
val isTLReadRxLen = io.tla.fire & io.tla.bits.address(6,0) === "h18".U & ( io.tla.bits.opcode === 4.U )
val isTLReadRxFifo = io.tla.fire & io.tla.bits.address(6,0) === "h1c".U & ( io.tla.bits.opcode === 4.U )
val rxLen = RegInit(0.U(32.W))
// val isRxBusy = RegInit(false.B)
@@ -139,10 +140,10 @@ trait TLCDRRx{ this: TLCDRBase =>
rxCnt := rxCnt + 1.U
rxData := Mux1H(Seq(
(rxCnt === 0.U) -> Cat( 0.U(24.W), CDRIn.io.axis.bits.tdata )
(rxCnt === 1.U) -> Cat( 0.U(16.W), CDRIn.io.axis.bits.tdata, rxData( 7,0) )
(rxCnt === 2.U) -> Cat( 0.U(8.W ), CDRIn.io.axis.bits.tdata, rxData(15,0) )
// (rxCnt === 3.U) -> Cat( CDRIn.io.axis.bits.tdata, rxData(23,0) )
(rxCnt === 0.U) -> Cat( 0.U(24.W), CDRIn.io.axis.bits.tdata ),
(rxCnt === 1.U) -> Cat( 0.U(16.W), CDRIn.io.axis.bits.tdata, rxData( 7,0) ),
(rxCnt === 2.U) -> Cat( 0.U(8.W ), CDRIn.io.axis.bits.tdata, rxData(15,0) ),
// (rxCnt === 3.U) -> Cat( CDRIn.io.axis.bits.tdata, rxData(23,0) ),
))
}
@@ -152,12 +153,12 @@ trait TLCDRRx{ this: TLCDRBase =>
rxLen := rxLen + 1.U
}
rxFifo.io.enq.valid := CDRIn.io.axis.fire & ( rxCnt === 3.U | CDRIn.io.axis.bits.last )
rxFifo.io.enq.valid := CDRIn.io.axis.fire & ( rxCnt === 3.U | CDRIn.io.axis.bits.tlast )
rxFifo.io.enq.bits := Mux1H(Seq(
(rxCnt === 0.U) -> Cat( 0.U(24.W), CDRIn.io.axis.bits.tdata )
(rxCnt === 1.U) -> Cat( 0.U(16.W), CDRIn.io.axis.bits.tdata, rxData( 7,0) )
(rxCnt === 2.U) -> Cat( 0.U(8.W ), CDRIn.io.axis.bits.tdata, rxData(15,0) )
(rxCnt === 3.U) -> Cat( CDRIn.io.axis.bits.tdata, rxData(23,0) )
(rxCnt === 0.U) -> Cat( 0.U(24.W), CDRIn.io.axis.bits.tdata ),
(rxCnt === 1.U) -> Cat( 0.U(16.W), CDRIn.io.axis.bits.tdata, rxData( 7,0) ),
(rxCnt === 2.U) -> Cat( 0.U(8.W ), CDRIn.io.axis.bits.tdata, rxData(15,0) ),
(rxCnt === 3.U) -> Cat( CDRIn.io.axis.bits.tdata, rxData(23,0) ),
))
CDRIn.io.axis.ready := true.B