ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

编译通过 仿真启动 请知悉 改处理器没有csr

Browse Source
This commit is contained in:
RuigeLee
2024-10-25 17:46:21 +08:00
parent 4737700f56
commit 78d54d2083
20 changed files with 880 additions and 69 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/resources/picorv32.v
View File

@@ -81,7 +81,7 @@ module picorv32 #(
parameter [ 0:0] REGS_INIT_ZERO = 0,
parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
parameter [31:0] PROGADDR_RESET = 32'h 8000_0000,
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
parameter [31:0] STACKADDR = 32'h ffff_ffff
) (

65
src/main/scala/backBoard/pico/BackSystem.scala
View File

@@ -4,15 +4,18 @@ import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import sifive.blocks.devices.uart._
import sifive.blocks.devices.gpio._
abstract class BackModule(implicit val p: Parameters) extends Module with HasBackParameters { def io: Record }
abstract class BackBundle(implicit val p: Parameters) extends Bundle with HasBackParameters
case object BackParamsKey extends Field[BackSetting]
case class BackSetting(
){
@@ -26,7 +29,9 @@ trait HasBackParameters {
class BackCfg extends Config((_, _, _) => {
case BackParamsKey => BackSetting()
})
@@ -60,35 +65,32 @@ class BackSys()(implicit p: Parameters) extends LazyModule with HasBackParameter
beatBytes = 32/8)))
val sram = LazyModule(new TLRAM(
address = Seq(AddressSet(0x80000000L, 0xffffL)),
address = AddressSet(0x80000000L, 0xffffL),
cacheable = false,
executable = true,
atomics = false,
beatBytes = 4,
ecc = ECCParams(),
sramReg = false, // drive SRAM data output directly into a register => 1 cycle longer response
))
val uart = LazyModule( new TLUART(
busWidthBytes = 4,
c = UARTParams(
address = BigInt(0x50000000L),
initBaudRate = BigInt(115200),
divinit = 0
)) )
// val uart = LazyModule( new TLUART(
// busWidthBytes = 4,
// params = UARTParams(
// address = BigInt(0x50000000L),
// initBaudRate = BigInt(115200),
// ), divinit = 0) )
val gpio = LazyModule(new TLGPIO(busWidthBytes = 4, c = GPIOParams(
address = BigInt(0x60000000L),
width = 16,
)))
// val gpio = LazyModule(new TLGPIO(busWidthBytes = 4, params = GPIOParams(
// address = BigInt(0x60000000L),
// width = 16,
// )))
val xbar = TLXbar()
xbar := coreClientNode
cdrNode := xbar
sram := xbar
uart := xbar
gpio := xbar
sram.node := xbar
@@ -96,8 +98,8 @@ class BackSys()(implicit p: Parameters) extends LazyModule with HasBackParameter
lazy val module: BackSysImp = new BackSysImp(this)
}
class BackSysImp(outer: BackSubSys) extends LazyModuleImp(outer) with HasBackParameters {
class BackSubSysIO extends Bundle{
class BackSysImp(outer: BackSys) extends LazyModuleImp(outer) with HasBackParameters {
class BackSysIO extends Bundle{
val overCLK = Input(Bool())
val uDatIn = Input(Bool())
val uDatOut = Output(Bool())
@@ -109,7 +111,7 @@ class BackSysImp(outer: BackSubSys) extends LazyModuleImp(outer) with HasBackPar
val ( cdr_bus, cdr_edge ) = outer.cdrNode.in.head
val io: BackSubSysIO = IO(new BackSubSysIO)
val io: BackSysIO = IO(new BackSysIO)
val pico = Module(new Picorv32_tl(edge = core_edge))
val cdr = for( i <- 0 until 2 ) yield { Module(new TLCDR(cdr_edge)) }
@@ -127,9 +129,9 @@ class BackSysImp(outer: BackSubSys) extends LazyModuleImp(outer) with HasBackPar
cdr(1).io.overCLK := io.overCLK
cdr(0).io.datIn := io.uDatIn
io.uDatOut := cdr(0).io.uDatOut
io.uDatOut := cdr(0).io.datOut
cdr(1).io.datIn := io.dDatIn
io.dDatOut := cdr(1).io.uDatOut
io.dDatOut := cdr(1).io.datOut
pico.io.tld.bits := core_bus.d.bits
@@ -142,17 +144,18 @@ class BackSysImp(outer: BackSubSys) extends LazyModuleImp(outer) with HasBackPar
cdr(0).io.tla.valid := cdr_bus.a.valid & cdr_bus.a.address(7) === "h0".U
cdr(1).io.tla.valid := cdr_bus.a.valid & cdr_bus.a.address(7) === "h1".U
cdr(0).io.tla.valid := cdr_bus.a.valid & cdr_bus.a.bits.address(7) === "h0".U
cdr(1).io.tla.valid := cdr_bus.a.valid & cdr_bus.a.bits.address(7) === "h1".U
cdr(0).io.tla.bits := cdr_bus.a.bits
cdr(1).io.tla.bits := cdr_bus.a.bits
cdr_bus.a.ready :=
(cdr_bus.a.address(7) === "h0".U & cdr(0).io.tla.ready) |
(cdr_bus.a.address(7) === "h1".U & cdr(1).io.tla.ready)
(cdr_bus.a.bits.address(7) === "h0".U & cdr(0).io.tla.ready) |
(cdr_bus.a.bits.address(7) === "h1".U & cdr(1).io.tla.ready)
cdr_bus.d.valid := cdr(0).io.tld.valid | cdr(1).io.tld.valid
cdr_bus.d.bits := Mux1H(Seq(
cdr(0).io.tld.valid -> cdr(0).io.tld.bits
cdr(1).io.tld.valid -> cdr(1).io.tld.bits
cdr(0).io.tld.valid -> cdr(0).io.tld.bits,
cdr(1).io.tld.valid -> cdr(1).io.tld.bits,
))
assert( ~(cdr(0).io.tld.valid & cdr(1).io.tld.valid), "Assert Failed! Two CDR can never resp at the same cycle!" )

17
src/main/scala/backBoard/pico/Picorv32_tl.scala
View File

@@ -3,10 +3,12 @@ package BACK
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
class Picorv32_tl(edge: TLEdgeOut)(implicit p: Parameters) extends BackModule {
val io = IO(new Bundle {
class Picorv32_tl(edge: TLEdgeOut)(implicit p: Parameters) extends BackModule{
class Picorv32IO_tl extends Bundle{
val trap = Output(Bool())
val tla = new DecoupledIO(new TLBundleA(edge.bundle))
@@ -14,11 +16,11 @@ class Picorv32_tl(edge: TLEdgeOut)(implicit p: Parameters) extends BackModule {
val irq = Input(UInt(32.W))
val eoi = Output(UInt(32.W))
}
})
val io: Picorv32IO_tl = IO(new Picorv32IO_tl)
val core = Module(new Picorv32)
val core = Module(new picorv32)
core.io.clk := clock.asBool
core.io.resetn := ~reset.asBool
@@ -43,7 +45,7 @@ class Picorv32_tl(edge: TLEdgeOut)(implicit p: Parameters) extends BackModule {
val tlaValid = RegInit(false.B)
when( io.tlaClient.fire ){
when( io.tla.fire ){
tlaValid := false.B
} .elsewhen( tlStateCurr === 0.U & tlStateNext === 1.U ){
tlaValid := true.B
@@ -52,6 +54,7 @@ class Picorv32_tl(edge: TLEdgeOut)(implicit p: Parameters) extends BackModule {
core.io.mem_ready := io.tld.fire
core.io.mem_rdata := io.tld.bits.data
io.tld.ready := true.B
io.tla.valid := tlaValid
when( core.io.mem_wstrb.orR ){
io.tla.bits :=

41
src/main/scala/backBoard/pico/TLCDR.scala
View File

@@ -4,7 +4,8 @@ import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.amba.axi4._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
abstract class TLCDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends BackModule {
@@ -18,14 +19,14 @@ abstract class TLCDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends Bac
val tld = new DecoupledIO(new TLBundleD(edge.bundle))
}
val io: TLCDRIO: IO(new TLCDRIO)
val io: TLCDRIO = IO(new TLCDRIO)
val CDRIn = Module(new CDRIn)
CDRIn.io.serDat := io.datIn
CDRIn.io.overCLK := io.overCLK
val CDROut = Module(new CDROut)
io.datOut := CDROut.io serDat
io.datOut := CDROut.io.serDat
// CDRIn.io.axis = Decoupled(new AXIS_Bundle(8))
@@ -40,9 +41,9 @@ abstract class TLCDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends Bac
trait TLCDRTx{ this: TLCDRBase =>
val isTLReadTxStatus = io.tla.fire & io.tla.bits.address(7,0) === "h0".U & ( io.tla.bits.opcode === 4.U )
val isTLWriteTxLen = io.tla.fire & io.tla.bits.address(7,0) === "h4".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val isTLWriteTxFifo = io.tla.fire & io.tla.bits.address(7,0) === "h8".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val isTLReadTxStatus = io.tla.fire & io.tla.bits.address(6,0) === "h0".U & ( io.tla.bits.opcode === 4.U )
val isTLWriteTxLen = io.tla.fire & io.tla.bits.address(6,0) === "h4".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val isTLWriteTxFifo = io.tla.fire & io.tla.bits.address(6,0) === "h8".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val isTLWriteTxSoftReset = isTLWriteTxLen
@@ -72,7 +73,7 @@ trait TLCDRTx{ this: TLCDRBase =>
CDROut.io.axis.bits.tlast := txLen === 0.U & ~txFifo.io.deq.valid & txCnt === 3.U
CDROut.io.axis.bits.tuser := isTxError
CDROut.io.axis.bits.valid := isTxBusy
CDROut.io.axis.valid := isTxBusy
when( isTLWriteTxLen ){
@@ -115,10 +116,10 @@ trait TLCDRTx{ this: TLCDRBase =>
trait TLCDRRx{ this: TLCDRBase =>
val isTLWriteRxSoftReset = io.tla.fire & io.tla.bits.address(7,0) === "h10".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val isTLReadRxStatus = io.tla.fire & io.tla.bits.address(7,0) === "h14".U & ( io.tla.bits.opcode === 4.U )
val isTLReadRxLen = io.tla.fire & io.tla.bits.address(7,0) === "h18".U & ( io.tla.bits.opcode === 4.U )
val isTLReadRxFifo = io.tla.fire & io.tla.bits.address(7,0) === "h1c".U & ( io.tla.bits.opcode === 4.U )
val isTLWriteRxSoftReset = io.tla.fire & io.tla.bits.address(6,0) === "h10".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val isTLReadRxStatus = io.tla.fire & io.tla.bits.address(6,0) === "h14".U & ( io.tla.bits.opcode === 4.U )
val isTLReadRxLen = io.tla.fire & io.tla.bits.address(6,0) === "h18".U & ( io.tla.bits.opcode === 4.U )
val isTLReadRxFifo = io.tla.fire & io.tla.bits.address(6,0) === "h1c".U & ( io.tla.bits.opcode === 4.U )
val rxLen = RegInit(0.U(32.W))
// val isRxBusy = RegInit(false.B)
@@ -139,10 +140,10 @@ trait TLCDRRx{ this: TLCDRBase =>
rxCnt := rxCnt + 1.U
rxData := Mux1H(Seq(
(rxCnt === 0.U) -> Cat( 0.U(24.W), CDRIn.io.axis.bits.tdata )
(rxCnt === 1.U) -> Cat( 0.U(16.W), CDRIn.io.axis.bits.tdata, rxData( 7,0) )
(rxCnt === 2.U) -> Cat( 0.U(8.W ), CDRIn.io.axis.bits.tdata, rxData(15,0) )
// (rxCnt === 3.U) -> Cat( CDRIn.io.axis.bits.tdata, rxData(23,0) )
(rxCnt === 0.U) -> Cat( 0.U(24.W), CDRIn.io.axis.bits.tdata ),
(rxCnt === 1.U) -> Cat( 0.U(16.W), CDRIn.io.axis.bits.tdata, rxData( 7,0) ),
(rxCnt === 2.U) -> Cat( 0.U(8.W ), CDRIn.io.axis.bits.tdata, rxData(15,0) ),
// (rxCnt === 3.U) -> Cat( CDRIn.io.axis.bits.tdata, rxData(23,0) ),
))
}
@@ -152,12 +153,12 @@ trait TLCDRRx{ this: TLCDRBase =>
rxLen := rxLen + 1.U
}
rxFifo.io.enq.valid := CDRIn.io.axis.fire & ( rxCnt === 3.U | CDRIn.io.axis.bits.last )
rxFifo.io.enq.valid := CDRIn.io.axis.fire & ( rxCnt === 3.U | CDRIn.io.axis.bits.tlast )
rxFifo.io.enq.bits := Mux1H(Seq(
(rxCnt === 0.U) -> Cat( 0.U(24.W), CDRIn.io.axis.bits.tdata )
(rxCnt === 1.U) -> Cat( 0.U(16.W), CDRIn.io.axis.bits.tdata, rxData( 7,0) )
(rxCnt === 2.U) -> Cat( 0.U(8.W ), CDRIn.io.axis.bits.tdata, rxData(15,0) )
(rxCnt === 3.U) -> Cat( CDRIn.io.axis.bits.tdata, rxData(23,0) )
(rxCnt === 0.U) -> Cat( 0.U(24.W), CDRIn.io.axis.bits.tdata ),
(rxCnt === 1.U) -> Cat( 0.U(16.W), CDRIn.io.axis.bits.tdata, rxData( 7,0) ),
(rxCnt === 2.U) -> Cat( 0.U(8.W ), CDRIn.io.axis.bits.tdata, rxData(15,0) ),
(rxCnt === 3.U) -> Cat( CDRIn.io.axis.bits.tdata, rxData(23,0) ),
))
CDRIn.io.axis.ready := true.B

2
src/main/scala/backBoard/pico/picorv32.scala
View File

@@ -7,7 +7,7 @@ import chisel3.experimental._
class Picorv32 extends BlackBox() with HasBlackBoxResource {
class picorv32 extends BlackBox() with HasBlackBoxResource {
val io = IO(new Bundle {
val clk = Input(Bool())
val resetn = Input(Bool())

16
src/test/scala/gcd/test.scala
View File

@@ -54,9 +54,19 @@ object testModule extends App {
// ChiselGeneratorAnnotation(() => { new ShinSlvBase })
// ))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new picorv32_tl })
))
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
// ChiselGeneratorAnnotation(() => { new picorv32_tl })
// ))
val cfg = new BackCfg
(new chisel3.stage.ChiselStage).execute( Array("--show-registrations", "--full-stacktrace", "--target-dir", "generated/cdr/", "-e", "verilog") ++ args, Seq(
ChiselGeneratorAnnotation(() => {
val soc = LazyModule(new BackSys()(cfg))
soc.module
})
))
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(