From 784bad548a5fad17a09921cabf6167dd85f5df96 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Fri, 16 May 2025 20:22:51 +0800 Subject: [PATCH] =?UTF-8?q?islastdev=E4=BD=93=E7=8E=B0=E5=AF=84=E5=AD=98?= =?UTF-8?q?=E5=99=A8=E4=BF=AE=E6=94=B9?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/SlaveParser.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index 4aeeb04..73d0653 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -100,7 +100,7 @@ abstract class SlaveParserBase extends Module{ // val isDevOnLeft = RegInit(0.U(2.W)); io.isDevOnLeft := isDevOnLeft val isDevOnLeftModify = RegInit(false.B); io.isDevOnLeftModify := isDevOnLeftModify val indexOfLeftDev = RegInit(0.U(14.W)); io.indexOfLeftDev := indexOfLeftDev - io.isDevOnRight := Mux( isLastDevice, "b01".U, "b10".U ) + io.isDevOnRight := Mux( isLastDevice, "b00".U, "b01".U ) val isDevOnRightModify = RegInit(false.B); io.isDevOnRightModify := isDevOnRightModify val indexOfRightDev = RegInit(0.U(14.W)); io.indexOfRightDev := indexOfRightDev