时序优化

src/main/scala/backBoard/shin/ShinSlv.scala

@@ -73,6 +73,7 @@ trait ShinSlvPhyDownStreamRecv{ this: ShinSlvPhyBase =>
 
   val downOldHead = Reg( new Header_Info_Bundle )
   val downNewHead = Reg( new Header_Info_Bundle )
+  val downNewHeadShift = Reg( new Header_Info_Bundle )
 
   val downPendBuf= Module( new Queue( new AXIS_Bundle(8), 2, pipe = true, flow = false ) with chisel3.util.experimental.InlineInstance)
   downStreamCdrIn.io.axis <> downPendBuf.io.enq
@@ -185,6 +186,7 @@ trait ShinSlvPhyDownStreamSend{ this: ShinSlvPhyBase =>
   val isLastDevice: Bool
   val downForwardDataByte: UInt
   val downNewHead: Header_Info_Bundle
+  val downNewHeadShift: Header_Info_Bundle
   val isDownStreamError: Bool
 
 
@@ -193,12 +195,12 @@ trait ShinSlvPhyDownStreamSend{ this: ShinSlvPhyBase =>
 
   downSendStateNext := Mux1H(Seq(
     ( downSendStateCurr === DownSendStateIdle  ) -> Mux( isDownNewHeadCreated & ~isLastDevice, DownSendStateNHead, DownSendStateIdle ),
-    ( downSendStateCurr === DownSendStateNHead ) -> Mux( downSendCnt === ((headByte)-1).U & downStreamCdrOut.io.axis.fire,       DownSendStateFData, DownSendStateNHead ),
+    ( downSendStateCurr === DownSendStateNHead ) -> Mux( downSendCnt === ((headByte)).U & downStreamCdrOut.io.axis.fire,       DownSendStateFData, DownSendStateNHead ),
-    ( downSendStateCurr === DownSendStateFData ) -> Mux( downSendCnt === (downForwardDataByte -1.U) & downStreamCdrOut.io.axis.fire, DownSendStateIdle,  DownSendStateFData),
+    ( downSendStateCurr === DownSendStateFData ) -> Mux( downSendCnt === (downForwardDataByte ) & downStreamCdrOut.io.axis.fire, DownSendStateIdle,  DownSendStateFData),
   ))
 
   when( downSendStateCurr =/= downSendStateNext ){
-    downSendCnt := 0.U
+    downSendCnt := 1.U
   } .elsewhen( downStreamCdrOut.io.axis.fire ){
     downSendCnt := downSendCnt + 1.U
   }
@@ -207,10 +209,20 @@ trait ShinSlvPhyDownStreamSend{ this: ShinSlvPhyBase =>
     downSendStateCurr === DownSendStateNHead | downSendStateCurr === DownSendStateFData
 
   downStreamCdrOut.io.axis.bits.tdata := Mux1H(Seq(
-    ( downSendStateCurr === DownSendStateNHead ) -> (downNewHead.asUInt << (downSendCnt << 3)).apply(63,56),
+    ( downSendStateCurr === DownSendStateNHead ) -> downNewHeadShift.asUInt(63,56),
     ( downSendStateCurr === DownSendStateFData ) -> downForwardFifo.io.deq.bits.tdata,
   ))
 
+  val downOldHead: Header_Info_Bundle
+  val downLocalDataByte: UInt
+  when( isDownNewHeadCreated ){
+    downNewHeadShift.length   := Mux( downOldHead.length >= downLocalDataByte, downOldHead.length - downLocalDataByte, 0.U )
+    downNewHeadShift.operator := downOldHead.operator
+    downNewHeadShift.param    := downOldHead.param
+  } .elsewhen( downStreamCdrOut.io.axis.fire & downSendStateCurr === DownSendStateNHead ){
+    downNewHeadShift := (downNewHeadShift.asUInt << 8).asTypeOf(new Header_Info_Bundle)
+  }
+
   downStreamCdrOut.io.axis.bits.tlast := ( downSendStateCurr === DownSendStateFData ) & downForwardFifo.io.deq.bits.tlast
 
 
@@ -252,13 +264,13 @@ trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
 
   upRecvStateNext := Mux1H(Seq(
     (upRecvStateCurr === UpRecvStateIdle ) -> Mux( upPendBuf.io.deq.valid, UpRecvStateOHead, UpRecvStateIdle ),
-    (upRecvStateCurr === UpRecvStateOHead) -> Mux( upPendBuf.io.deq.fire, Mux( ~upPendBuf.io.deq.bits.tlast, Mux( upRecvCnt === ((headByte)-1).U,         UpRecvStateFData, UpRecvStateOHead), UpRecvStateIdle), UpRecvStateOHead ),
+    (upRecvStateCurr === UpRecvStateOHead) -> Mux( upPendBuf.io.deq.fire, Mux( ~upPendBuf.io.deq.bits.tlast, Mux( upRecvCnt === ((headByte)).U,         UpRecvStateFData, UpRecvStateOHead), UpRecvStateIdle), UpRecvStateOHead ),
-    (upRecvStateCurr === UpRecvStateFData) -> Mux( upPendBuf.io.deq.fire, Mux( ~upPendBuf.io.deq.bits.tlast, Mux( upRecvCnt === (upOldHead.length - 1.U), UpRecvStateCRC,   UpRecvStateFData), UpRecvStateIdle), UpRecvStateFData ),
+    (upRecvStateCurr === UpRecvStateFData) -> Mux( upPendBuf.io.deq.fire, Mux( ~upPendBuf.io.deq.bits.tlast, Mux( upRecvCnt === (upOldHead.length), UpRecvStateCRC,   UpRecvStateFData), UpRecvStateIdle), UpRecvStateFData ),
     (upRecvStateCurr === UpRecvStateCRC  ) -> Mux( upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tlast, UpRecvStateIdle, UpRecvStateCRC ),
   ))
 
   when( upRecvStateCurr =/= upRecvStateNext){
-    upRecvCnt := 0.U
+    upRecvCnt := 1.U
   } .elsewhen( upPendBuf.io.deq.fire ){
     upRecvCnt := upRecvCnt + 1.U
   }
@@ -313,7 +325,7 @@ trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
     upRecvStateCurr === UpRecvStateFData & upPendBuf.io.deq.fire
   upForwardFifo.io.enq.bits.tdata := upPendBuf.io.deq.bits.tdata
   upForwardFifo.io.enq.bits.tuser := upPendBuf.io.deq.bits.tuser
-  upForwardFifo.io.enq.bits.tlast := upRecvCnt === (upForwardDataByte -1.U) | upPendBuf.io.deq.bits.tlast
+  upForwardFifo.io.enq.bits.tlast := upRecvCnt === (upForwardDataByte) | upPendBuf.io.deq.bits.tlast
 
 
   upPendBuf.io.deq.ready := 
@@ -339,7 +351,7 @@ trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
   } .elsewhen( upRecvStateCurr === UpRecvStateFData & upRecvStateNext === UpRecvStateIdle ){
     isUpStreamError := true.B
     printf("Warning, Wrong Package Received in UpStream, That could not happened!\n")
-  } .elsewhen( upRecvStateCurr === UpRecvStateCRC & upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tlast & upRecvCnt =/= 3.U ){
+  } .elsewhen( upRecvStateCurr === UpRecvStateCRC & upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tlast & upRecvCnt =/= 4.U ){
     isUpStreamError := true.B
     printf("Warning, Wrong Package Received in UpStream, That could not happened!\n")
   }
@@ -375,29 +387,40 @@ trait ShinSlvPhyUpStreamSend{ this: ShinSlvPhyDownStream =>
 
   upSendStateNext := Mux1H(Seq(
     ( upSendStateCurr === UpSendStateIdle  ) -> Mux( isUpNewHeadCreated, UpSendStateNHead, UpSendStateIdle ),
-    ( upSendStateCurr === UpSendStateNHead ) -> Mux( upSendCnt === ((headByte)-1).U & upStreamCdrOut.io.axis.fire,          UpSendStateLData, UpSendStateNHead),
+    ( upSendStateCurr === UpSendStateNHead ) -> Mux( upSendCnt === ((headByte)).U & upStreamCdrOut.io.axis.fire,          UpSendStateLData, UpSendStateNHead),
-    ( upSendStateCurr === UpSendStateLData ) -> Mux( upSendCnt === (upLocalDataByte   - 1.U) & upStreamCdrOut.io.axis.fire, Mux( isLastDevice, UpSendStateIdle, UpSendStateFData), UpSendStateLData),
+    ( upSendStateCurr === UpSendStateLData ) -> Mux( upSendCnt === (upLocalDataByte) & upStreamCdrOut.io.axis.fire, Mux( isLastDevice, UpSendStateIdle, UpSendStateFData), UpSendStateLData),
-    ( upSendStateCurr === UpSendStateFData ) -> Mux( upSendCnt === (upForwardDataByte - 1.U) & upStreamCdrOut.io.axis.fire, UpSendStateIdle,  UpSendStateFData),
+    ( upSendStateCurr === UpSendStateFData ) -> Mux( upSendCnt === (upForwardDataByte) & upStreamCdrOut.io.axis.fire, UpSendStateIdle,  UpSendStateFData),
   ))
 
   when( upSendStateCurr =/= upSendStateNext ){
-    upSendCnt := 0.U
+    upSendCnt := 1.U
   } .elsewhen( upStreamCdrOut.io.axis.fire ){
     upSendCnt := upSendCnt + 1.U
   }
 
 
-
+  val upNewHeadShift = Reg(new Header_Info_Bundle)
 
   upStreamCdrOut.io.axis.valid :=
     upSendStateCurr === UpSendStateNHead | upSendStateCurr === UpSendStateLData | upSendStateCurr === UpSendStateFData
 
   upStreamCdrOut.io.axis.bits.tdata := Mux1H(Seq(
-    ( upSendStateCurr === UpSendStateNHead ) -> (upNewHead.asUInt << (upSendCnt << 3)).apply(63,56),
+    ( upSendStateCurr === UpSendStateNHead ) -> upNewHeadShift.asUInt(63,56),
-    ( upSendStateCurr === UpSendStateLData ) -> upReg(upSendCnt),
+    ( upSendStateCurr === UpSendStateLData ) -> upReg(upSendCnt-1.U),
     ( upSendStateCurr === UpSendStateFData ) -> upForwardFifo.io.deq.bits.tdata,
   ))
 
+  val upOldHead: Header_Info_Bundle
+  when( isUpNewHeadCreated ){
+    upNewHeadShift.length   := upOldHead.length + upLocalDataByte
+    upNewHeadShift.operator := upOldHead.operator
+    upNewHeadShift.param    := upOldHead.param
+  } .elsewhen( upStreamCdrOut.io.axis.fire & upSendStateCurr === UpSendStateNHead ){
+    upNewHeadShift := (upNewHeadShift.asUInt << 8).asTypeOf(new Header_Info_Bundle)
+  }
+
+
+
   upStreamCdrOut.io.axis.bits.tlast := ( upSendStateCurr === UpSendStateFData ) & upForwardFifo.io.deq.bits.tlast
 
   upStreamCdrOut.io.axis.bits.tuser :=
@@ -537,7 +560,7 @@ with ShinSlvLinkUCast{
 
 
   val led = IO(UInt(8.W))
-  led := slvID
+  led := RegEnable( 1.U << slvID, 0.U, ~RegNext(isInit) & isInit)
 }