主站加入定时器，fifo被迫加大

src/main/scala/backBoard/pico/TLCDR.scala

@@ -35,8 +35,8 @@ abstract class TLCDRBase()(implicit p: Parameters) extends BackModule {
 
 
 
-  val txFifo = Module(new Queue(UInt(32.W), 4))
+  val txFifo = Module(new Queue(UInt(32.W), 8))
-  val rxFifo = Module(new Queue(UInt(32.W), 4))
+  val rxFifo = Module(new Queue(UInt(32.W), 8))
 
 }
 

tb/backSys_tb.v

@@ -104,7 +104,7 @@ initial begin
 
 	reset <= 0;
 
-	# 1000000
+	# 5000000
 			$display("Time Out !!!");
 	$stop;
 end

tb/sw/src/MstMain.c

@@ -49,6 +49,14 @@ void main()
 		*cdr_softReset = 1; //复位脉冲
 		*cdr_direct = 0;
 
+		asm volatile ( //timer 2s
+			"1:\n"
+			"rdcycle ra\n"
+			"srli ra, ra, 12\n"
+			//"srli ra, ra, 26\n"
+			"andi ra, ra, 0x1\n"
+			"beqz ra, 1b\n"
+		);
 
 
 		//发送下行包头
@@ -127,6 +135,5 @@ void main()
 
 		totNum = (upRecvLen >> 3);
 
-		while(1);
 	}
 }

tb/sw/src/SlvMain.c

@@ -49,7 +49,6 @@ void main()
 		isLast = *ReadIsLast;
 		*cdr_direct = 0;
 
-
 		asm volatile (
 			"1:\n"
 			"andi ra, sp, 0x04\n"