主站加入定时器，fifo被迫加大

src/main/scala/backBoard/pico/TLCDR.scala

@@ -35,8 +35,8 @@ abstract class TLCDRBase()(implicit p: Parameters) extends BackModule {
 
 
 
-  val txFifo = Module(new Queue(UInt(32.W), 4))
-  val rxFifo = Module(new Queue(UInt(32.W), 4))
+  val txFifo = Module(new Queue(UInt(32.W), 8))
+  val rxFifo = Module(new Queue(UInt(32.W), 8))
 
 }