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对顶层文件中的错误修改,使得仿真可以正常运行

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This commit is contained in:
bacon
2025-09-08 18:51:26 +08:00
parent fa1327aa5f
commit 73b773e286
3 changed files with 7 additions and 7 deletions
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2
tb/shinTest/ShinTopSpiTb.v
View File

@@ -672,7 +672,7 @@ task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,in
len = (txBuf[_pos + 4] & 8'h0f) * 256 + (txBuf[_pos + 5] & 8'hff);
end else begin
addr_type = rxBuf[_pos + 1] & 8'h3;
dev = (txBuf[_pos] * 256) >> 2;
dev = (rxBuf[_pos] * 256) >> 2;
dev = dev + ((rxBuf[_pos + 1] >> 2) & 8'hff);
addr = rxBuf[_pos + 2] * 256 + (rxBuf[_pos + 3] & 8'hff);
cmd = (rxBuf[_pos + 4] >> 4) & 8'h0f;

10
tb/shinTest/ShinTopSpiTb_clk.v
View File

@@ -603,11 +603,11 @@ always @(posedge sck) begin
if( &bitCnt ) begin
byteCnt <= byteCnt +1;
transCnt <= transCnt + 1;
if( txBuf[2] === 1 & nextByteCnt >= 4) begin
if( txBuf[2] === 8'h80 & nextByteCnt >= 4) begin
rxBuf[byteCnt] <= exChangeRegi;
//$display("spi read out %x", exChangeRegi);
end
if( txBuf[2] === 1 & nextByteCnt >= 3) begin
if( txBuf[2] === 8'h80 & nextByteCnt >= 4) begin
exChangeRegi <= isQspi ? {exChangeRegi[3:0], qspi_mux_miso} : {exChangeRegi[6:0], spi_mux_miso};
end else begin
exChangeRegi <= 0;
@@ -696,8 +696,8 @@ task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,in
len = (txBuf[_pos + 4] & 8'h0f) * 256 + (txBuf[_pos + 5] & 8'hff);
end else begin
addr_type = rxBuf[_pos + 1] & 8'h3;
dev = (txBuf[_pos] * 256) >> 2;
dev = dev + ((txBuf[_pos + 1] >> 2) & 8'hff);
dev = (rxBuf[_pos] * 256) >> 2;
dev = dev + ((rxBuf[_pos + 1] >> 2) & 8'hff);
addr = rxBuf[_pos + 2] * 256 + (rxBuf[_pos + 3] & 8'hff);
cmd = (rxBuf[_pos + 4] >> 4) & 8'h0f;
len = (rxBuf[_pos + 4] & 8'h0f) * 256 + (rxBuf[_pos + 5] & 8'hff);
@@ -964,7 +964,7 @@ task wait_comm_finished(input [16:0] dev_idx);
$display("error occur");
is_run = 0;
end
if (($realtime - st) >= 500000000000.0)
if (($realtime - st) >= 1000000000000.0)
begin
$display("comm timeout.");
is_run = 0;

2
tb/shinTest/gen_pkt.py
View File

@@ -9,7 +9,7 @@ if __name__ == '__main__':
#add_tc_2_runlist(rwregs.tc1())
#'''
'''
add_tc_2_runlist(errorPkt.tc1())
add_tc_2_runlist(errorPkt.tc2())
add_tc_2_runlist(errorPkt.tc3())