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Merge branch 'ShinTop' into eb_dev

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bacon
2025-05-16 17:30:29 +08:00
parent a32cd3c8c7 0a772e4efc
commit 7369d13f35
4 changed files with 158 additions and 30 deletions
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125
tb/shinTest/ShinTopSpiTb.v
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@@ -517,7 +517,7 @@ initial begin
//子报文
txBuf[132+3] = 8'h0;
txBuf[133+3] = 8'hc; //index = 3
txBuf[134+3] = 8'h09; //地址 //SM1
txBuf[134+3] = 8'h10; //地址 //SM1
txBuf[135+3] = 8'h40; //地址 //偏置
txBuf[136+3] = 8'h00; //命令0 长度56
txBuf[137+3] = 8'd56; //长度
@@ -624,7 +624,7 @@ initial begin
//写入替换时间戳替换地址
txBuf[0+3] = 8'h0c;
txBuf[1+3] = 8'hc0;
spi_trans( (16'h25), (`SPI_WRITE), (2), (0) ); //写入SM1
spi_trans( (16'h25), (`SPI_WRITE), (2), (0) ); //写入替换时间戳替换地址寄存器
//发布请求
txBuf[0+3] = 8'h18;
@@ -635,8 +635,129 @@ initial begin
spi_trans( (16'h20), (`SPI_WRITE), (1), (0) );//发送SM0 接收SM0, 请求发送
@(posedge isResp) #5 begin end
//清除替换时间戳替换地址
txBuf[0+3] = 8'h00;
txBuf[1+3] = 8'h00;
spi_trans( (16'h25), (`SPI_WRITE), (2), (0) ); //清除替换时间戳替换地址寄存器
//设定sync信号
//设置SM1在写入51地址触发enq
txBuf[0+3] = 8'd51;
txBuf[1+3] = 8'h00;
spi_trans( (16'h0202), (`SPI_WRITE), (2), (0) );
//header
txBuf[0+3] = 8'h03;
txBuf[1+3] = 8'h00;//heeader length 48
txBuf[2+3] = 8'h00;
txBuf[3+3] = 8'h00;
//子报文
//设置同步相关寄存器
txBuf[4+3] = 8'h0; //设备索引
txBuf[5+3] = 8'h08; //设备索引、类型 //2号设备
txBuf[6+3] = 8'h01; //地址
txBuf[7+3] = 8'h20; //地址 0x120
txBuf[8+3] = 8'h10; //命令1 写入寄存器 负载长度2
txBuf[9+3] = 8'h28; //负载长度0x28
txBuf[10+3] = 8'h0; //工作计数0
txBuf[11+3] = 8'h0; //工作计数0
// txBuf[12+3] = 8'h0f; //负载0x120 0x0f 全部脉冲，全部使能
// txBuf[13+3] = 0; //负载0x121
// txBuf[14+3] = 10; //负载0x122 sync0脉冲宽度 10
// txBuf[15+3] = 0; //负载0x123
// txBuf[16+3] = 0; //负载0x124 sync1脉冲宽度 0
// txBuf[17+3] = 0; //负载0x125
// txBuf[18+3] = 1; //负载0x126 sync2脉冲宽度 1
// txBuf[19+3] = 0; //负载0x127
// txBuf[20+3] = 8'hff; //负载0x128 sync3脉冲宽度 最大
// txBuf[21+3] = 8'hff; //负载0x129
txBuf[12+3] = 8'hff; //负载0x120 0xff 全部电平，全部使能
txBuf[13+3] = 0; //负载0x121
txBuf[14+3] = 0; //负载0x122 sync0脉冲宽度
txBuf[15+3] = 0; //负载0x123
txBuf[16+3] = 0; //负载0x124 sync1脉冲宽度
txBuf[17+3] = 0; //负载0x125
txBuf[18+3] = 0; //负载0x126 sync2脉冲宽度
txBuf[19+3] = 0; //负载0x127
txBuf[20+3] = 0; //负载0x128 sync3脉冲宽度
txBuf[21+3] = 0; //负载0x129
txBuf[22+3] = 0; //负载0x12a empty
txBuf[23+3] = 0; //负载0x12b
txBuf[24+3] = 0; //负载0x12c
txBuf[25+3] = 0; //负载0x12d
txBuf[26+3] = 0; //负载0x12e
txBuf[27+3] = 0; //负载0x12f
//同步点
txBuf[28+3] = 8'h90; //负载0x130 同步点
txBuf[29+3] = 8'h88; //负载0x131
txBuf[30+3] = 0; //负载0x132
txBuf[31+3] = 0; //负载0x133
txBuf[32+3] = 0; //负载0x134
txBuf[33+3] = 0; //负载0x135
txBuf[34+3] = 0; //负载0x136
txBuf[35+3] = 0; //负载0x137
//周期
txBuf[36+3] = 8'hff; //负载0x138
txBuf[37+3] = 8'hf; //负载0x139
txBuf[38+3] = 0; //负载0x13a
txBuf[39+3] = 0; //负载0x13b
//0ffset sync1
txBuf[40+3] = 8'ha; //负载0x13c
txBuf[41+3] = 0; //负载0x13d
txBuf[42+3] = 0; //负载0x13e
txBuf[43+3] = 0; //负载0x13f
//0ffset sync2
txBuf[44+3] = 8'h0; //负载0x140
txBuf[45+3] = 0; //负载0x141
txBuf[46+3] = 0; //负载0x142
txBuf[47+3] = 0; //负载0x143
//0ffset sync3
txBuf[48+3] = 8'h0; //负载0x144
txBuf[49+3] = 8'h01; //负载0x145
txBuf[50+3] = 0; //负载0x146
txBuf[51+3] = 0; //负载0x147
spi_trans( (16'h1000), (`SPI_WRITE), (52), (0) ); //写入SM1
//发布请求
txBuf[0+3] = 8'd52;
txBuf[1+3] = 8'h00;
spi_trans( (16'h21), (`SPI_WRITE), (2), (0) );//写入长度
txBuf[0+3] = 8'h01;
spi_trans( (16'h20), (`SPI_WRITE), (1), (0) );//发送SM0 接收SM0, 请求发送
@(posedge isResp) #5 begin end
end
//清脉冲
//设置SM1在写入19地址触发enq
txBuf[0+3] = 0; //负载0x122 sync0脉冲宽度
txBuf[1+3] = 0; //负载0x123
txBuf[2+3] = 0; //负载0x124 sync1脉冲宽度
txBuf[3+3] = 0; //负载0x125
txBuf[4+3] = 0; //负载0x126 sync2脉冲宽度
txBuf[5+3] = 0; //负载0x127
txBuf[6+3] = 0; //负载0x128 sync3脉冲宽度
txBuf[7+3] = 0; //负载0x129
spi_trans( (16'h0122), (`SPI_WRITE), (8), (2) ); //slv2
end