From 7338314c17f30443b0d761b3b8ec9f6d96b26402 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Mon, 11 Aug 2025 19:33:56 +0800 Subject: [PATCH] =?UTF-8?q?4=E5=A4=9A=E7=9B=B8=E4=BD=8D=E6=95=88=E6=9E=9C?= =?UTF-8?q?=E6=98=8E=E6=98=BE=E6=9B=B4=E5=A5=BD?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/ebus/CDRIn.scala | 12 ++++++------ src/main/scala/backBoard/shin/ShinTop.scala | 2 +- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala index 1f3a0f1..222c451 100644 --- a/src/main/scala/backBoard/ebus/CDRIn.scala +++ b/src/main/scala/backBoard/ebus/CDRIn.scala @@ -70,21 +70,21 @@ trait CDRInMultiSample{ this: CDRInBase => //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先 - val multiCLK = IO(Input(Vec(16, Bool()))) + val multiCLK = IO(Input(Vec(4, Bool()))) - val sampleReg = Wire(Vec(23, Bool())) + val sampleReg = Wire(Vec(5, Bool())) - for( i <- 0 until 16 ) { + for( i <- 0 until 4 ) { sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) } } - for( i <- 16 until 23 ){ - sampleReg(i) := withClockAndReset(multiCLK(i-8).asClock, reset.asBool){ RegNext(sampleReg(i-8))} + for( i <- 4 until 5 ){ + sampleReg(i) := withClockAndReset(multiCLK(i-1).asClock, reset.asBool){ RegNext(sampleReg(i-1))} } - val asyncSerDat = PopCount(sampleReg) >= 12.U + val asyncSerDat = PopCount(sampleReg) >= 3.U // sampleReg.count( (x: Bool) => (x === true.B) ) >= 12.U diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala index 45638a1..d5513d4 100644 --- a/src/main/scala/backBoard/shin/ShinTop.scala +++ b/src/main/scala/backBoard/shin/ShinTop.scala @@ -11,7 +11,7 @@ class ShinTopIO extends Bundle{ val uDatIn = Input(Bool()) val uDatOut = Output(Bool()) - val multiCLK = Input(Vec(16, Bool())) + val multiCLK = Input(Vec(4, Bool())) val iqspi = new QSPIInterfaceIO val ospi = new SSPIInterfaceIO