diff --git a/src/main/scala/backBoard/shin/SpiInterface.scala b/src/main/scala/backBoard/shin/SpiInterface.scala
index 3111274..0b3b5ac 100644
--- a/src/main/scala/backBoard/shin/SpiInterface.scala
+++ b/src/main/scala/backBoard/shin/SpiInterface.scala
@@ -151,7 +151,7 @@ class QSpiInterface extends SpiInterfaceBase{
   sck       := qspi.sck
   csn       := qspi.csn
   qspi.miso := exRego(7, 4)
-  qspi.isDirIn := isSpiWrite
+  qspi.isDirIn := ~isSpiRead
 
   when( shiftCSn(2) & ~shiftCSn(1) ){
     bitSel := 0.U
diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v
index b64a6b4..cd65420 100644
--- a/tb/shinTest/ShinTopSpiTb.v
+++ b/tb/shinTest/ShinTopSpiTb.v
@@ -327,15 +327,9 @@ wire [11:0] nextByteCnt = byteCnt + 1;
 always @(negedge sck) begin
   if( isBusy ) begin      
     if( &bitCnt ) begin
-      if( txBuf[2] === 1 & nextByteCnt >= 3) begin
-        exChangeRego <= isQspi ? exChangeRego << 4 : exChangeRego << 1;
-      end else begin
-        exChangeRego <= txBuf[nextByteCnt];
-      end
+      exChangeRego <= txBuf[nextByteCnt];
     end else begin
-      if( isQspi ) begin
-        exChangeRego <= isQspi ? exChangeRego << 4 : exChangeRego << 1;
-      end
+      exChangeRego <= isQspi ? exChangeRego << 4 : exChangeRego << 1;
     end
   end
 end