ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

准备QEI和Spi

Browse Source
This commit is contained in:
RuigeLee
2024-06-11 18:29:02 +08:00
parent 46090a6460
commit 715a1e6c08
5 changed files with 279 additions and 183 deletions
Download Patch File Download Diff File Expand all files Collapse all files

138
src/main/scala/backBoard/DIn16.scala Normal file
View File

@@ -0,0 +1,138 @@
package BACK
import chisel3._
import chisel3.util._
trait BackBoardSlvIn16 { this: BackBoardSlvLocal =>
val inPin = Wire(UInt(16.W))
val flitCnt = RegInit(MixedVecInit(Seq( false.B, 0.U(4.W), false.B, false.B, false.B, false.B, false.B, false.B, false.B) ))
val flitTrigger = Wire(Vec(9, Bool()))
val digitalFilter = for( i <- 0 until 2 ) yield { RegInit( 1.U(8.W) ) }
val digitalIn = for( i <- 0 until 2 ) yield { Reg( Vec(8, Bool()) ) }
flitTrigger(0) := ~RegNext(flitTrigger(0))
flitTrigger(1) := flitCnt(1) === 15.U
when( ~RegNext(usTrigger) & usTrigger ){
flitCnt(1) := flitCnt(1) + 1.U
}
flitTrigger(2) := flitCnt(2)
when( ~RegNext(flitTrigger(1)) & flitTrigger(1) ){
flitCnt(2) := ~flitCnt(2)
}
flitTrigger(3) := flitCnt(3)
when( ~RegNext(flitTrigger(2)) & flitTrigger(2) ){
flitCnt(3) := ~flitCnt(3)
}
flitTrigger(4) := flitCnt(4)
when( ~RegNext(flitTrigger(3)) & flitTrigger(3) ){
flitCnt(4) := ~flitCnt(4)
}
flitTrigger(5) := flitCnt(5)
when( ~RegNext(flitTrigger(4)) & flitTrigger(4) ){
flitCnt(5) := ~flitCnt(5)
}
flitTrigger(6) := flitCnt(6)
when( ~RegNext(flitTrigger(5)) & flitTrigger(5) ){
flitCnt(6) := ~flitCnt(6)
}
flitTrigger(7) := flitCnt(7)
when( ~RegNext(flitTrigger(6)) & flitTrigger(6) ){
flitCnt(7) := ~flitCnt(7)
}
flitTrigger(8) := flitCnt(8)
when( ~RegNext(flitTrigger(7)) & flitTrigger(7) ){
flitCnt(8) := ~flitCnt(8)
}
for( i <- 0 until 8 ) {
for( j <- 0 until 2 ) {
val flitter = RegInit(VecInit( Seq.fill(16){false.B}))
val flitHi = RegInit(0.U((log2Ceil(16)).W))
val shiftIn = RegNext( inPin(i+8*j) )
val sample =
Mux( digitalFilter(j) === 1.U, ~RegNext(flitTrigger(1)) & flitTrigger(1),
Mux(digitalFilter(j) === 2.U, ~RegNext(flitTrigger(2)) & flitTrigger(2),
Mux(digitalFilter(j) === 3.U, ~RegNext(flitTrigger(3)) & flitTrigger(3),
Mux(digitalFilter(j) === 4.U, ~RegNext(flitTrigger(4)) & flitTrigger(4),
Mux(digitalFilter(j) === 5.U, ~RegNext(flitTrigger(5)) & flitTrigger(5),
Mux(digitalFilter(j) === 6.U, ~RegNext(flitTrigger(6)) & flitTrigger(6),
Mux(digitalFilter(j) === 7.U, ~RegNext(flitTrigger(7)) & flitTrigger(7),
Mux(digitalFilter(j) === 8.U, ~RegNext(flitTrigger(8)) & flitTrigger(8), true.B
))))))))
when( sample ){
flitter(0) := shiftIn
(1 until 16).map{ k =>
flitter(k) := flitter(k-1)
}
when( ~flitter(15) & flitter(0) ){
flitHi := flitHi + 1.U
} .elsewhen( flitter(15) & ~flitter(0) ){
flitHi := flitHi - 1.U
}
when( flitHi === 12.U ){
digitalIn(j)(i) := true.B
} .elsewhen( flitHi === 3.U ){
digitalIn(j)(i) := false.B
}
// val fliterCnt = WireDefault( VecInit( (1 until 16).map{ k => flitter(k) }) )
// assert( flitHi <= 15.U )
// assert( fliterCnt.count( (k:Bool) => k === true.B ) === flitHi )
}
}
}
}
class DIn16 extends BackBoardSlvLocal
with BackBoardSlvStatusPR
with BackBoardSlvIn16{
val in = IO(Input(UInt(16.W)))
inPin := in
when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){
digitalFilter(0) := downRegTemp(4)
digitalFilter(1) := downRegTemp(5)
}
val digitalInSync = for( i <- 0 until 2 ) yield { RegEnable( Cat( digitalIn(i).reverse ), isUpdate ) }
when( statusPage === 0.U ){
upReg(2) := digitalInSync(0)
upReg(3) := digitalInSync(1)
upReg(4) := digitalFilter(0)
upReg(5) := digitalFilter(1)
}
}

57
src/main/scala/backBoard/Dout16.scala Normal file
View File

@@ -0,0 +1,57 @@
package BACK
import chisel3._
import chisel3.util._
trait BackBoardSlvOut16{ this: BackBoardSlvLocal =>
val outRegSync = Wire(UInt(16.W))
val mthodReg = RegInit(0.U(16.W))
val valueReg = RegInit(0.U(16.W))
val outPin = Wire(UInt(16.W))
outPin :=
Mux(statusPR === 3.U, outRegSync, (mthodReg & valueReg) | (~mthodReg & outRegSync))
}
class DOut16 extends BackBoardSlvLocal
with BackBoardSlvStatusPR
with BackBoardSlvOut16{
val out = IO(Output(UInt(16.W)))
val flt = IO(Input(Vec(2, Bool())))
val outReg = RegInit(0.U(16.W))
when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){
outReg := Cat(downRegTemp(3), downRegTemp(2))
}
when( isCrcPass & downRegTemp(0)(3,0) === 1.U & downRegTemp(2).extract(0) ){
mthodReg := Cat(downRegTemp(3), downRegTemp(2))
valueReg := Cat(downRegTemp(5), downRegTemp(4))
}
outRegSync := RegEnable( outReg, 0.U, isUpdate )
when( statusPage === 0.U ){
upReg(2) := outReg(7,0)
upReg(3) := outReg(15,8)
upReg(4) := Cat( ~flt(1), ~flt(0) )
}
when( statusPage === 1.U ){
upReg(2) := RegEnable(downRegTemp(2).extract(0), isCrcPass & downRegTemp(0)(3,0) === 1.U)
upReg(4) := mthodReg(7,0)
upReg(5) := mthodReg(15,8)
upReg(6) := valueReg(7,0)
upReg(7) := valueReg(15,8)
}
out := outPin
}

183
src/main/scala/backBoard/LocalRegisters.scala
View File

@@ -101,191 +101,8 @@ trait BackBoardSlvStatusPR { this: BackBoardSlvLocal =>
trait BackBoardSlvIn16 { this: BackBoardSlvLocal =>
val inPin = Wire(UInt(16.W))
val flitCnt = RegInit(MixedVecInit(Seq( false.B, 0.U(4.W), false.B, false.B, false.B, false.B, false.B, false.B, false.B) ))
val flitTrigger = Wire(Vec(9, Bool()))
val digitalFilter = for( i <- 0 until 2 ) yield { RegInit( 1.U(8.W) ) }
val digitalIn = for( i <- 0 until 2 ) yield { Reg( Vec(8, Bool()) ) }
flitTrigger(0) := ~RegNext(flitTrigger(0))
flitTrigger(1) := flitCnt(1) === 15.U
when( ~RegNext(usTrigger) & usTrigger ){
flitCnt(1) := flitCnt(1) + 1.U
}
flitTrigger(2) := flitCnt(2)
when( ~RegNext(flitTrigger(1)) & flitTrigger(1) ){
flitCnt(2) := ~flitCnt(2)
}
flitTrigger(3) := flitCnt(3)
when( ~RegNext(flitTrigger(2)) & flitTrigger(2) ){
flitCnt(3) := ~flitCnt(3)
}
flitTrigger(4) := flitCnt(4)
when( ~RegNext(flitTrigger(3)) & flitTrigger(3) ){
flitCnt(4) := ~flitCnt(4)
}
flitTrigger(5) := flitCnt(5)
when( ~RegNext(flitTrigger(4)) & flitTrigger(4) ){
flitCnt(5) := ~flitCnt(5)
}
flitTrigger(6) := flitCnt(6)
when( ~RegNext(flitTrigger(5)) & flitTrigger(5) ){
flitCnt(6) := ~flitCnt(6)
}
flitTrigger(7) := flitCnt(7)
when( ~RegNext(flitTrigger(6)) & flitTrigger(6) ){
flitCnt(7) := ~flitCnt(7)
}
flitTrigger(8) := flitCnt(8)
when( ~RegNext(flitTrigger(7)) & flitTrigger(7) ){
flitCnt(8) := ~flitCnt(8)
}
for( i <- 0 until 8 ) {
for( j <- 0 until 2 ) {
val flitter = RegInit(VecInit( Seq.fill(16){false.B}))
val flitHi = RegInit(0.U((log2Ceil(16)).W))
val shiftIn = RegNext( inPin(i+8*j) )
val sample =
Mux( digitalFilter(j) === 1.U, ~RegNext(flitTrigger(1)) & flitTrigger(1),
Mux(digitalFilter(j) === 2.U, ~RegNext(flitTrigger(2)) & flitTrigger(2),
Mux(digitalFilter(j) === 3.U, ~RegNext(flitTrigger(3)) & flitTrigger(3),
Mux(digitalFilter(j) === 4.U, ~RegNext(flitTrigger(4)) & flitTrigger(4),
Mux(digitalFilter(j) === 5.U, ~RegNext(flitTrigger(5)) & flitTrigger(5),
Mux(digitalFilter(j) === 6.U, ~RegNext(flitTrigger(6)) & flitTrigger(6),
Mux(digitalFilter(j) === 7.U, ~RegNext(flitTrigger(7)) & flitTrigger(7),
Mux(digitalFilter(j) === 8.U, ~RegNext(flitTrigger(8)) & flitTrigger(8), true.B
))))))))
when( sample ){
flitter(0) := shiftIn
(1 until 16).map{ k =>
flitter(k) := flitter(k-1)
}
when( ~flitter(15) & flitter(0) ){
flitHi := flitHi + 1.U
} .elsewhen( flitter(15) & ~flitter(0) ){
flitHi := flitHi - 1.U
}
when( flitHi === 12.U ){
digitalIn(j)(i) := true.B
} .elsewhen( flitHi === 3.U ){
digitalIn(j)(i) := false.B
}
// val fliterCnt = WireDefault( VecInit( (1 until 16).map{ k => flitter(k) }) )
// assert( flitHi <= 15.U )
// assert( fliterCnt.count( (k:Bool) => k === true.B ) === flitHi )
}
}
}
}
class DIn16 extends BackBoardSlvLocal
with BackBoardSlvStatusPR
with BackBoardSlvIn16{
val in = IO(Input(UInt(16.W)))
inPin := in
when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){
digitalFilter(0) := downRegTemp(4)
digitalFilter(1) := downRegTemp(5)
}
val digitalInSync = for( i <- 0 until 2 ) yield { RegEnable( Cat( digitalIn(i).reverse ), isUpdate ) }
when( statusPage === 0.U ){
upReg(2) := digitalInSync(0)
upReg(3) := digitalInSync(1)
upReg(4) := digitalFilter(0)
upReg(5) := digitalFilter(1)
}
}
trait BackBoardSlvOut16{ this: BackBoardSlvLocal =>
val outRegSync = Wire(UInt(16.W))
val mthodReg = RegInit(0.U(16.W))
val valueReg = RegInit(0.U(16.W))
val outPin = Wire(UInt(16.W))
outPin :=
Mux(statusPR === 3.U, outRegSync, (mthodReg & valueReg) | (~mthodReg & outRegSync))
}
class DOut16 extends BackBoardSlvLocal
with BackBoardSlvStatusPR
with BackBoardSlvOut16{
val out = IO(Output(UInt(16.W)))
val flt = IO(Input(Vec(2, Bool())))
val outReg = RegInit(0.U(16.W))
when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){
outReg := Cat(downRegTemp(3), downRegTemp(2))
}
when( isCrcPass & downRegTemp(0)(3,0) === 1.U & downRegTemp(2).extract(0) ){
mthodReg := Cat(downRegTemp(3), downRegTemp(2))
valueReg := Cat(downRegTemp(5), downRegTemp(4))
}
outRegSync := RegEnable( outReg, 0.U, isUpdate )
when( statusPage === 0.U ){
upReg(2) := outReg(7,0)
upReg(3) := outReg(15,8)
upReg(4) := Cat( ~flt(1), ~flt(0) )
}
when( statusPage === 1.U ){
upReg(2) := RegEnable(downRegTemp(2).extract(0), isCrcPass & downRegTemp(0)(3,0) === 1.U)
upReg(4) := mthodReg(7,0)
upReg(5) := mthodReg(15,8)
upReg(6) := valueReg(7,0)
upReg(7) := valueReg(15,8)
}
out := outPin
}

49
src/main/scala/backBoard/Qei.scala Normal file
View File

@@ -0,0 +1,49 @@
package BACK
import chisel3._
import chisel3.util._
trait BackBoardSlvQei{ this: BackBoardSlvLocal =>
val phaseA = Wire(Bool())
val phaseB = Wire(Bool())
val counter = Reg(UInt(32.W))
val encordNxt = Cat( phaseB, phaseA )
val encordCur = RegNext(encordNxt)
val isCheckDirect = Wire(Bool())
val is2Multi = Wire(Bool())
val is4Multi = Wire(Bool())
val isAdvA =
( encordCur === "b00".U & encordNxt === "b01".U ) |
( encordCur === "b01".U & encordNxt === "b11".U ) |
( encordCur === "b11".U & encordNxt === "b10".U ) |
( encordCur === "b10".U & encordNxt === "b00".U )
val isAdvB =
( encordNxt === "b00".U & encordCur === "b01".U ) |
( encordNxt === "b01".U & encordCur === "b11".U ) |
( encordNxt === "b11".U & encordCur === "b10".U ) |
( encordNxt === "b10".U & encordCur === "b00".U )
val isMiss = encordCur === ~encordNxt
val isKeep = encordCur === encordNxt
when(){
when( isMiss ){
printf("Warning! QEI Miss one pulse!\n")
} .elsewhen( isAdvA ){
} .elsewhen( isAdvB ){
} .otherwise{
assert( isKeep )
}
}
}

35
src/main/scala/backBoard/SpiSlv.scala Normal file
View File

@@ -0,0 +1,35 @@
package BACK
import chisel3._
import chisel3.util._
trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
val sck = Wire(Bool())
val mosi = Wire(Bool())
val csn = Wire(Bool())
val clk100M = Wire(Bool())
val shiftSCK = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(sck, 3, false.B, true.B) }
val shiftCSn = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(csn, 3, true.B, true.B) }
val shiftMOSI = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(mosi, 3) }
val isSckPosedge = ~shiftSCK(2) & shiftSCK(1)
val isSckNegedge = shiftSCK(2) & ~shiftSCK(1)
val downReg_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(8*8.W)) }
val upReg_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(8*8.W)) }
val misoReg = withClockAndReset( clk100M.asClock, reset ){ Reg(Bool()) }
withClockAndReset( clk100M.asClock, reset ){//100M
when( isSckPosedge & shiftCSn(2) ){
misoReg := downReg_100M.extract(0)
downReg_100M := downReg_100M >> 1
upReg_100M := Cat( upReg_100M(8*8-1,1), shiftMOSI(2) )
}
}
}