准备QEI和Spi

src/main/scala/backBoard/SpiSlv.scala

@@ -0,0 +1,35 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+
+trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
+  val sck = Wire(Bool())
+  val mosi = Wire(Bool())
+  val csn   = Wire(Bool())
+  val clk100M = Wire(Bool())
+
+  val shiftSCK  = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(sck, 3, false.B, true.B) }
+  val shiftCSn  = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(csn, 3, true.B, true.B) }
+  val shiftMOSI = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(mosi, 3) }
+
+  val isSckPosedge = ~shiftSCK(2) & shiftSCK(1)
+  val isSckNegedge = shiftSCK(2) & ~shiftSCK(1)
+
+
+  val downReg_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(8*8.W)) }
+  val upReg_100M   = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(8*8.W)) }
+  val misoReg      = withClockAndReset( clk100M.asClock, reset ){ Reg(Bool()) }
+
+
+  withClockAndReset( clk100M.asClock, reset ){//100M
+    when( isSckPosedge & shiftCSn(2) ){
+      misoReg := downReg_100M.extract(0)
+      downReg_100M := downReg_100M >> 1
+      upReg_100M := Cat( upReg_100M(8*8-1,1), shiftMOSI(2) )
+    }
+  }
+
+}
+