准备QEI和Spi

This commit is contained in:
RuigeLee
2024-06-11 18:29:02 +08:00
parent 46090a6460
commit 715a1e6c08
5 changed files with 279 additions and 183 deletions

View File

@@ -0,0 +1,49 @@
package BACK
import chisel3._
import chisel3.util._
trait BackBoardSlvQei{ this: BackBoardSlvLocal =>
val phaseA = Wire(Bool())
val phaseB = Wire(Bool())
val counter = Reg(UInt(32.W))
val encordNxt = Cat( phaseB, phaseA )
val encordCur = RegNext(encordNxt)
val isCheckDirect = Wire(Bool())
val is2Multi = Wire(Bool())
val is4Multi = Wire(Bool())
val isAdvA =
( encordCur === "b00".U & encordNxt === "b01".U ) |
( encordCur === "b01".U & encordNxt === "b11".U ) |
( encordCur === "b11".U & encordNxt === "b10".U ) |
( encordCur === "b10".U & encordNxt === "b00".U )
val isAdvB =
( encordNxt === "b00".U & encordCur === "b01".U ) |
( encordNxt === "b01".U & encordCur === "b11".U ) |
( encordNxt === "b11".U & encordCur === "b10".U ) |
( encordNxt === "b10".U & encordCur === "b00".U )
val isMiss = encordCur === ~encordNxt
val isKeep = encordCur === encordNxt
when(){
when( isMiss ){
printf("Warning! QEI Miss one pulse!\n")
} .elsewhen( isAdvA ){
} .elsewhen( isAdvB ){
} .otherwise{
assert( isKeep )
}
}
}