准备QEI和Spi

src/main/scala/backBoard/Dout16.scala

@@ -0,0 +1,57 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+
+trait BackBoardSlvOut16{ this: BackBoardSlvLocal =>
+
+  val outRegSync  = Wire(UInt(16.W))
+
+  val mthodReg = RegInit(0.U(16.W))
+  val valueReg = RegInit(0.U(16.W))
+
+  val outPin = Wire(UInt(16.W))
+
+  outPin := 
+    Mux(statusPR === 3.U, outRegSync, (mthodReg & valueReg) | (~mthodReg & outRegSync))
+
+}
+
+
+class DOut16 extends BackBoardSlvLocal
+with BackBoardSlvStatusPR
+with BackBoardSlvOut16{
+  val out = IO(Output(UInt(16.W)))
+  val flt = IO(Input(Vec(2, Bool())))
+  val outReg  = RegInit(0.U(16.W))
+
+  when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){
+    outReg := Cat(downRegTemp(3), downRegTemp(2))
+  }
+  when( isCrcPass & downRegTemp(0)(3,0) === 1.U & downRegTemp(2).extract(0) ){
+    mthodReg := Cat(downRegTemp(3), downRegTemp(2))
+    valueReg := Cat(downRegTemp(5), downRegTemp(4))
+  }
+
+  outRegSync := RegEnable( outReg, 0.U, isUpdate )
+
+  when( statusPage === 0.U ){
+    upReg(2) := outReg(7,0)
+    upReg(3) := outReg(15,8)
+    upReg(4) := Cat( ~flt(1), ~flt(0) )
+  }
+
+  when( statusPage === 1.U ){
+    upReg(2) := RegEnable(downRegTemp(2).extract(0), isCrcPass & downRegTemp(0)(3,0) === 1.U)
+
+    upReg(4) := mthodReg(7,0)
+    upReg(5) := mthodReg(15,8)
+    upReg(6) := valueReg(7,0)
+    upReg(7) := valueReg(15,8)
+  }
+
+  out := outPin
+
+}
+