diff --git a/src/main/verilog/backBoardMstTop.v b/src/main/verilog/backBoardMstTop.v
new file mode 100644
index 0000000..480d19d
--- /dev/null
+++ b/src/main/verilog/backBoardMstTop.v
@@ -0,0 +1,111 @@
+////////////////////////
+//LVDS-BUS SYSTEM DEMO//
+////////////////////////
+
+module master_top(
+  input resetn,
+  input clock, 
+    
+  input lvds_up_din_p,
+  input lvds_up_din_n, 
+           
+  output lvds_down_dout_p,
+  output lvds_down_dout_n,
+     
+  input  [12:0] io_FSMC_addr,
+  input  [7:0]  io_FSMC_dataIn,
+  output [7:0]  io_FSMC_dataOut,
+  output        io_FSMC_dataOEn,
+  input         io_FSMC_cen,
+  input         io_FSMC_oen,
+  input         io_FSMC_wen
+
+);
+
+wire clk_400m;
+wire clk_100m;
+wire clk_50m;
+wire clk_50m_a;
+wire clk_10m;
+
+reg        rst_n;
+
+wire       lvds_down_dout;
+wire       lvds_up_din;
+
+reg        rstn_d;
+
+
+
+
+
+
+always@(posedge clk_10m) begin
+    rstn_d <= resetn;
+	rst_n <= rstn_d;
+end
+
+
+Gowin_rPLL u_Gowin_rPLL(
+  .clkout(clk_400m), //pll clkout,400MHz
+  .clkoutd(clk_100m), //100MHz
+  .clkin(clock) //clkin,50MHz
+);
+
+
+Gowin_rPLL1 u_Gowin_rPLL1(
+  .clkout(clk_50m), //output clkout
+  .lock(), //output lock
+  .clkin(clock) //input clkin
+);
+
+
+TLVDS_OBUF lvds_downstream_out(
+  .O(lvds_down_dout_p),
+  .OB(lvds_down_dout_n),
+  .I(lvds_down_dout)
+);
+
+
+TLVDS_IBUF lvds_upstream_in(
+  .O(lvds_up_din),
+  .I(lvds_up_din_p),
+  .IB(lvds_up_din_n)
+);
+
+
+defparam Inst5_CLKDIVC.DIV_MODE = "5" ;
+CLKDIV Inst5_CLKDIVC(
+  .RESETN (1'b1  ),
+  .HCLKIN (clk_50m),
+  .CALIB  (1'b0     ),
+  .CLKOUT (clk_10m  )
+);
+
+
+BackBoardMst i_BackBoardMst(
+    .io_FSMC_addr(io_FSMC_addr),
+    .io_FSMC_dataIn(io_FSMC_dataIn),
+    .io_FSMC_dataOut(io_FSMC_dataOut),
+    .io_FSMC_dataOEn(io_FSMC_dataOEn),
+    .io_FSMC_cen(io_FSMC_cen),
+    .io_FSMC_oen(io_FSMC_oen),
+    .io_FSMC_wen(io_FSMC_wen),
+
+    .io_reset(~rst_n),
+
+    .io_oser_pclk(clk_10m), 
+    .io_oser_fclk(clk_50m),  
+    .io_ides_pclk(clk_100m),
+    .io_ides_fclk(clk_400m),
+
+    .io_lvds_down_dout(lvds_down_dout),
+    .io_lvds_up_din(lvds_up_din)
+);
+
+
+
+
+
+
+endmodule
\ No newline at end of file
diff --git a/src/main/verilog/backBoardSlvTop.v b/src/main/verilog/backBoardSlvTop.v
new file mode 100644
index 0000000..0140989
--- /dev/null
+++ b/src/main/verilog/backBoardSlvTop.v
@@ -0,0 +1,113 @@
+
+
+module slave_top(
+
+  input resetn,
+  input clock, 
+     
+  input  lvds_up_din_p,
+  input  lvds_up_din_n, 
+  output lvds_up_dout_p,
+  output lvds_up_dout_n,  
+           
+  input  lvds_down_din_p,
+  input  lvds_down_din_n,  
+  output lvds_down_dout_p,
+  output lvds_down_dout_n,
+
+  input  [31:0] in,
+  output [31:0] out,
+  output [31:0] oe
+);
+
+wire clk_400m;
+wire clk_100m;
+wire clk_50m;
+wire clk_10m;
+
+
+reg        rst_n;
+reg        rstn_d;
+
+
+always@(posedge clk_10m) begin
+    rstn_d <= resetn;
+	rst_n <= rstn_d;
+end
+
+
+Gowin_rPLL u_Gowin_rPLL(
+  .clkout(clk_400m), //pll clkout,400MHz
+  .clkoutd(clk_100m), //100MHz
+  .clkin(clock) //clkin,50MHz
+);
+
+
+Gowin_rPLL1 u_Gowin_rPLL1(
+  .clkout(clk_50m), //output clkout
+  .lock(), //output lock
+  .clkin(clkin) //input clkin
+);
+
+
+TLVDS_OBUF lvds_downstream_out(
+  .O(lvds_down_dout_p),
+  .OB(lvds_down_dout_n),
+  .I(lvds_down_dout)
+);
+
+
+TLVDS_IBUF lvds_downstream_in(
+  .O(lvds_down_din),
+  .I(lvds_down_din_p),
+  .IB(lvds_down_din_n)
+);
+
+
+TLVDS_OBUF lvds_upstream_out(
+  .O(lvds_up_dout_p),
+  .OB(lvds_up_dout_n),
+  .I(lvds_up_dout)
+);
+
+
+TLVDS_IBUF lvds_upstream_in(
+  .O(lvds_up_din),
+  .I(lvds_up_din_p),
+  .IB(lvds_up_din_n)
+);
+
+
+defparam Inst5_CLKDIVC.DIV_MODE = "5" ;
+CLKDIV Inst5_CLKDIVC(
+  .RESETN (1'b1),
+  .HCLKIN (clk_50m),
+  .CALIB  (1'b0),
+  .CLKOUT (clk_10m)
+);
+
+
+BackBoardSlvDigitalIO i_BackBoardSlvDigitalIO(
+    .io_reset(~rst_n),
+
+    .io_oser_pclk(clk_10m),
+    .io_oser_fclk(clk_50m),
+    .io_ides_pclk(clk_100m),
+    .io_ides_fclk(clk_400m),
+
+    .io_lvds_down_din(lvds_down_din),
+    .io_lvds_down_dout(lvds_down_dout),
+    .io_lvds_up_din(lvds_up_din),
+    .io_lvds_up_dout(lvds_up_dout),
+
+    .in(in),
+    .out(out),
+    .oe(oe)
+);
+
+
+endmodule
+
+
+
+