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cleanup

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This commit is contained in:
RuigeLee
2023-10-24 15:34:30 +08:00
parent 86fb086bd2
commit 701ba16491
3 changed files with 5 additions and 56 deletions
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27
src/main/scala/Switch/mac/MAC.scala
View File

@@ -737,44 +737,29 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
val txReq_ToAsync = Wire(new AsyncBundle(new TxFifo_Stream_Bundle))
// val txResp_ToAsync = Wire(new AsyncBundle(Bool()))
// val fateTxRespPort = Wire( Flipped(Decoupled(Bool())) )
// fateTxReqPort.ready := true.B
// wishbone.io.txResp <> FromAsyncBundle( txResp_ToAsync )
txReq_ToAsync <> ToAsyncBundle( wishbone.io.txReq )
withClockAndReset(io.mii.mtx_clk_pad_i.asClock, io.asyncReset) {
// txResp_ToAsync <> ToAsyncBundle( macTileLinkTx.io.txResp )
macTileLinkTx.io.txReq <> FromAsyncBundle( txReq_ToAsync )
}
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
// val ReadTxDataFromFifo_sync = ShiftRegister( macTileLinkTx.io.ReadTxDataFromFifo_tck, 2, false.B, true.B)
// wishbone.io.ReadTxDataFromFifo_sync := ReadTxDataFromFifo_sync
withClockAndReset( io.mii.mtx_clk_pad_i.asClock, io.asyncReset ){
macTileLinkTx.io.BlockingTxStatusWrite_sync := ShiftRegister( wishbone.io.BlockingTxStatusWrite, 2, false.B, true.B)
// macTileLinkTx.io.TxStartFrm_sync := ShiftRegister( wishbone.io.TxStartFrm_wb, 2, false.B, true.B ) // Synchronizing TxStartFrm_wb to MTxClk
// macTileLinkTx.io.ReadTxDataFromFifo_syncb := ShiftRegister( ReadTxDataFromFifo_sync, 2, false.B, true.B)
}
// wishbone.io.TxStartFrm_syncb := ShiftRegister( macTileLinkTx.io.TxStartFrm_sync, 2, false.B, true.B )
RstDeferLatched := macTileLinkTx.io.RstDeferLatched
TxStartFrm := macTileLinkTx.io.TxStartFrm
TxEndFrm := macTileLinkTx.io.TxEndFrm
TxData := macTileLinkTx.io.TxData
// macTileLinkTx.io.TxData_wb := wishbone.io.TxData_wb
macTileLinkTx.io.TxEndFrm_wb := wishbone.io.TxEndFrm_wb
macTileLinkTx.io.TxEndFrm_wb := wishbone.io.TxEndFrm_wb
wishbone.io.TxUsedData := TxUsedData
macTileLinkTx.io.TxUsedData := TxUsedData
macTileLinkTx.io.TxUsedData := TxUsedData
macTileLinkTx.io.TxRetry := TxRetry
macTileLinkTx.io.TxAbort := TxAbort
@@ -814,9 +799,6 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
val RxAbortSync = ShiftRegister( macTileLinkRx.io.RxAbortLatched, 2, false.B, true.B )
wishbone.io.RxAbortSync := RxAbortSync
// val ShiftEndedSync = ShiftRegister( macTileLinkRx.io.ShiftEnded_rck, 2, false.B, true.B )
// wishbone.io.ShiftEndedSync := ShiftEndedSync
val req_ToAsync = Wire(new AsyncBundle(new RxFifo_Stream_Bundle))
@@ -848,10 +830,7 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
Busy_IRQ := Busy_IRQ_sync & ~RegNext(Busy_IRQ_sync, false.B)
withClockAndReset( io.mii.mrx_clk_pad_i.asClock, io.asyncReset ) {
// val ShiftEndedSyncb = ShiftRegister( ShiftEndedSync, 3, false.B, true.B) //async 3 cycle for protect wishbone.io.syncToBuf.valid
println("Warning, No protect in ShiftEndedSyncb?!")
RxStatusWriteLatchedSync := fateRxRespPort.fire
// macTileLinkRx.io.ShiftEndedSyncb := fateRxRespPort.fire
macTileLinkRx.io.RxAbortSyncb := ShiftRegister( RxAbortSync, 2, false.B, true.B )
macTileLinkRx.io.Busy_IRQ_syncb := ShiftRegister( Busy_IRQ_sync, 2, false.B, true.B )

16
src/main/scala/Switch/mac/MacTileLinkTx.scala
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@@ -16,10 +16,8 @@ class MacTileLinkTxIO extends Bundle{
// val txResp = Decoupled()
val RstDeferLatched = Output(Bool())
val BlockingTxStatusWrite_sync = Input(Bool())
// val TxStartFrm_sync = Input(Bool())
val TxStartFrm = Output(Bool()) // Transmit packet start frame
val TxEndFrm = Output(Bool()) // Transmit packet end frame
@@ -30,11 +28,8 @@ class MacTileLinkTxIO extends Bundle{
val TxAbort = Input(Bool()) // Transmit packet abort
val TxDone = Input(Bool()) // Transmission ended
// val ReadTxDataFromFifo_tck = Output(Bool())
// val ReadTxDataFromFifo_syncb = Input(Bool())
val TxEndFrm_wb = Input(Bool())
// val TxData_wb = Input(UInt(8.W))
}
@@ -89,17 +84,6 @@ class MacTileLinkTx extends Module with RequireAsyncReset{
// when(
// io.TxStartFrm_sync & ~TxStartFrm |
// io.TxUsedData & Flop & ~LastWord |
// TxStartFrm & io.TxUsedData & Flop ){
// ReadTxDataFromFifo_tck := true.B
// // TxData := io.TxData_wb( 7, 0)
//
// } .elsewhen(io.ReadTxDataFromFifo_syncb & ~RegNext(io.ReadTxDataFromFifo_syncb, false.B)){
// ReadTxDataFromFifo_tck := false.B
// }
io.txReq.ready :=
io.txReq.valid & io.txReq.bits.isStart & ~TxStartFrm |
io.TxUsedData & Flop & ~LastWord |

18
src/main/scala/Switch/mac/MacTilelink.scala
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@@ -23,24 +23,18 @@ abstract class MacTileLinkBase() extends Module{
val rxReq = Flipped(Decoupled(new RxFifo_Stream_Bundle))
val rxResp = Decoupled(new Bool())
// val RxDataLatched2_rxclk = Input(UInt(8.W))
// val WriteRxDataToFifoSync = Input(Bool())
val RxAbortSync = Input(Bool())
val LatchedRxLength_rxclk = Input(UInt(16.W))
val RxStatusInLatched_rxclk = Input(UInt(9.W))
// val ShiftEndedSync = Input(Bool())
val RxReady = Output(Bool())
val txReq = Decoupled(new TxFifo_Stream_Bundle)
// val TxStartFrm_wb = Output(Bool())
// val TxStartFrm_syncb = Input(Bool())
val TxEndFrm_wb = Output(Bool())
// val TxData_wb = Output(UInt(8.W))
// val ReadTxDataFromFifo_sync = Input(Bool())
// Tx Status signals
val RetryCntLatched = Input(UInt(4.W)) // Latched Retry Counter
@@ -75,7 +69,6 @@ abstract class MacTileLinkBase() extends Module{
val ShiftEndedSyncPluse = io.rxReq.bits.isLast & io.rxReq.fire
val RxAbortPluse = io.RxAbortSync & ~RegNext(io.RxAbortSync, false.B)
// val WriteRxDataToFifoSyncPluse = io.WriteRxDataToFifoSync & ~RegNext(io.WriteRxDataToFifoSync, false.B)
val RxReady = RegInit(false.B); io.RxReady := RxReady
@@ -137,7 +130,7 @@ abstract class MacTileLinkBase() extends Module{
val TxStartFrm_wb = RegInit(false.B); //io.TxStartFrm_wb := TxStartFrm_wb
val TxStartFrm_wb = RegInit(false.B)
val TxEndFrm_wb = RegInit(false.B); io.TxEndFrm_wb := TxEndFrm_wb
val TxLength = RegInit(0.U(16.W))
@@ -146,7 +139,6 @@ abstract class MacTileLinkBase() extends Module{
val txRetryPulse = io.TxRetrySync & ~RegNext(io.TxRetrySync, false.B)
val txDonePulse = io.TxDoneSync & ~RegNext(io.TxDoneSync, false.B)
val txAbortPulse = io.TxAbortSync & ~RegNext(io.TxAbortSync, false.B)
// val ReadTxDataFromFifoSyncPluse = io.ReadTxDataFromFifo_sync & ~RegNext(io.ReadTxDataFromFifo_sync, false.B)
io.PerPacketPad := RegEnable(io.txDeq.req.bits.PerPacketPad, false.B, io.txDeq.req.fire)
@@ -212,16 +204,10 @@ abstract class MacTileLinkBase() extends Module{
// io.TxData_wb := io.txDeq.data.bits
io.txReq.bits.data := io.txDeq.data.bits
io.txReq.bits.isStart := TxStartFrm_wb
io.txReq.valid := io.txDeq.data.valid
io.txDeq.data.ready := io.txReq.ready
// io.txDeq.data.ready := ReadTxDataFromFifoSyncPluse
// assert( ~(io.txDeq.data.ready & ~io.txDeq.data.valid), "Assert Failed, Tx should never under run!" )