new version

src/main/scala/backBoard/BackBoardMst.scala

@@ -21,7 +21,8 @@ class FSMC_Port_Bundle extends Bundle{
 class BackBoardMstIO extends Bundle{
   val FSMC = new FSMC_Port_Bundle
 
-  val reset     = Input(Bool())
+  // val reset     = Input(Bool())
+val reset_calib = Input(Bool())
   val oser_pclk = Input(Bool())
   val oser_fclk = Input(Bool())
         val ides_pclk = Input(Bool())
@@ -29,27 +30,70 @@ class BackBoardMstIO extends Bundle{
 
   val lvds_down_dout = Output(Bool())
   val lvds_up_din    = Input(Bool())
+
+  val cdrErr         = Output(Bool())
+  val crcErr         = Output(Bool())
+  val linkErr        = Output(Bool())
 }
 
+// class Master_Status_Bundle extends Bundle{
+//   val zero = UInt(11.W)
+//   val cdrErr         = Bool()
+//   val crcErr         = Bool()
+//   val linkErr        = Bool()
+//   val synchronize    = Bool()
+//   val initialization = Bool()
+// }
 
-class BackBoardMstBase extends RawModule{
+// class Master_Control_Bundle extends Bundle{
+//   val zero = UInt(13.W)
+//   val transmit       = Bool()
+//   val synchronize    = Bool()
+//   val initialization = Bool()
+// }
+
+
+class BackBoardMstBase extends Module{ //10M
   val io: BackBoardMstIO = IO(new BackBoardMstIO)
 
-
-
   val lvdsMst = Module(new Lvds_Bus_Master)
   val mirrorDown = Module(new MirrorSRAMDown())
   val mirrorUp   = Module(new MirrorSRAMUp())
 
-    val status  = Wire(UInt(16.W))
+  val statusCDRErr  = RegInit( false.B )
-    val slvNum  = Wire(UInt(5.W))
+  val statusCRCErr  = RegInit( false.B )
+  val statusLinkErr = RegInit( false.B )
+  val statusSynch   = RegInit( false.B )
+  val statusInit    = RegInit( false.B )
+
+  val ctrlTransmit = RegInit( false.B )
+  val ctrlCDRErr   = RegInit( false.B )
+  val ctrlCRCErr   = RegInit( false.B )
+  val ctrlLinkErr  = RegInit( false.B )
+  val ctrlSynch    = RegInit( false.B )
+  val ctrlInit     = RegInit( false.B )
+
+  val slvNum  = RegInit(0.U(6.W))
+  val slvOffLine = RegInit(0.U(6.W))
+
+  lvdsMst.io.rst_n       := ~reset.asBool
+  lvdsMst.io.reset_calib := io.reset_calib
+  lvdsMst.io.oser_pclk   := io.oser_pclk
+  lvdsMst.io.oser_fclk   := io.oser_fclk
+  lvdsMst.io.ides_pclk   := io.ides_pclk
+  lvdsMst.io.ides_fclk   := io.ides_fclk
+
+  io.lvds_down_dout      := lvdsMst.io.lvds_down_dout
+  lvdsMst.io.lvds_up_din := io.lvds_up_din
 
 
-  mirrorDown.io.clockw := io.ides_pclk.asBool
+
+
+  mirrorDown.io.clockw := io.oser_pclk.asBool
   mirrorDown.io.clockr := io.oser_pclk.asBool
 
   mirrorUp.io.clockw := io.oser_pclk.asBool
-  mirrorUp.io.clockr := io.ides_pclk.asBool
+  mirrorUp.io.clockr := io.oser_pclk.asBool
 
 }
 
@@ -58,9 +102,8 @@ class BackBoardMstBase extends RawModule{
 
 trait BackBoardMstFSMC{ this: BackBoardMstBase =>
 
-  withClockAndReset( io.ides_pclk.asClock, io.reset ){
+
-    val statusReg = RegInit(0.U(16.W)); status := statusReg
+
-    val slvNumReg = RegInit(1.U(5.W)); slvNum := slvNumReg
 
   val fsmcAddrSync   = ShiftRegister( io.FSMC.addr,   2, 0.U, true.B )
   val fsmcdataInSync = ShiftRegister( io.FSMC.dataIn, 2, 0.U, true.B )
@@ -90,53 +133,56 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
   io.FSMC.dataOut   := Mux( isAccessReg, regOut, mirrorUp.io.datar)
 
   regOut := Mux1H(Seq(
-      ( activeAddr === 0.U) -> status,
+    ( activeAddr === 0.U) -> 
-      ( activeAddr === 1.U) -> slvNum,
+      Cat(
+        statusCDRErr ,
+        statusCRCErr ,
+        statusLinkErr,
+        statusSynch  ,
+        statusInit
+      ),
+    ( activeAddr === 1.U) -> 
+      Cat(
+        ctrlTransmit,
+        ctrlCDRErr  ,
+        ctrlCRCErr  ,
+        ctrlLinkErr ,
+        ctrlSynch   ,
+        ctrlInit
+      ),
+    ( activeAddr === 2.U) -> slvNum,
+    ( activeAddr === 3.U) -> slvOffLine,
   ))
 
-    when( (~fsmcCEnSync & isAccessReg & (~fsmcWEnSync) ) & ( activeAddr === 0.U) ){
+
-      statusReg := fsmcdataInSync
+  // when( (~fsmcCEnSync & isAccessReg & (~fsmcWEnSync) ) & ( activeAddr === 0.U) ){
-    }
+  //   status := fsmcdataInSync
+  // }
 
   when( (~fsmcCEnSync & isAccessReg & (~fsmcWEnSync) ) & ( activeAddr === 1.U) ){
-      slvNumReg := fsmcdataInSync
+
+    ctrlTransmit := fsmcdataInSync.extract(5)
+    ctrlCDRErr   := fsmcdataInSync.extract(4)
+    ctrlCRCErr   := fsmcdataInSync.extract(3)
+    ctrlLinkErr  := fsmcdataInSync.extract(2)
+    ctrlSynch    := fsmcdataInSync.extract(1)
+    ctrlInit     := fsmcdataInSync.extract(0)
   }
 
+  // when( (~fsmcCEnSync & isAccessReg & (~fsmcWEnSync) ) & ( activeAddr === 2.U) ){
+  //   slvNum := fsmcdataInSync
+  // }
+
+  when( (~fsmcCEnSync & isAccessReg & (~fsmcWEnSync) ) & ( activeAddr === 3.U) ){
+    slvOffLine := fsmcdataInSync
   }
 
 }
 
-trait BackBoardMstLVDS{ this: BackBoardMstBase =>
+abstract class BackBoardMstLVDSBase extends BackBoardMstBase with BackBoardMstFSMC{
-  lvdsMst.io.rst_n     := ~io.reset
-  lvdsMst.io.oser_pclk := io.oser_pclk
-  lvdsMst.io.oser_fclk := io.oser_fclk
-  lvdsMst.io.ides_pclk := io.ides_pclk
-  lvdsMst.io.ides_fclk := io.ides_fclk
-  
-  io.lvds_down_dout      := lvdsMst.io.lvds_down_dout
-  lvdsMst.io.lvds_up_din := io.lvds_up_din
-    
-  
-  lvdsMst.io.tx_start := false.B
-
-
-  val trigger_wire = Wire(Bool())
-  val stateCur_wire = Wire( UInt(4.W) )
-
-  withClockAndReset( io.oser_pclk.asClock, io.reset ){
-
-    val stateCur = RegInit(3.U(4.W))
-    stateCur_wire := stateCur
-
-
-    val ( _, trigger ) = Counter(Range( 0,1000) )
-    trigger_wire := trigger
-
-    val isSync = RegInit(false.B)
 
 
   val frame_info_update_en = RegInit(false.B)
-
   val slave_type_num       = RegInit(0.U(8.W))
   val slave_data_length    = RegInit(0.U(8.W))
   val tx_start             = RegInit(false.B)
@@ -146,6 +192,153 @@ trait BackBoardMstLVDS{ this: BackBoardMstBase =>
   lvdsMst.io.slave_data_length    := slave_data_length
   lvdsMst.io.tx_start := tx_start
 
+  val stateCur = RegInit(15.U(4.W))
+}
+
+
+trait BackBoardMstLVDSInitialization{ this: BackBoardMstLVDSBase =>
+
+  val isInitCntReset = ( ~RegNext(ctrlInit) & ctrlInit ) | (stateCur === 3.U) | (stateCur === 8.U)
+  val ( _, isInitTimeout ) = Counter(Range( 0,5200), ctrlInit, isInitCntReset)
+  val synchCnt = Reg(UInt(3.W))
+
+  when( isInitTimeout ){
+
+    stateCur := 0.U
+
+    frame_info_update_en := false.B
+    slave_type_num       := 0.U
+    slave_data_length    := 0.U
+
+    tx_start := false.B
+    
+  } .elsewhen( stateCur === 0.U ){
+    stateCur := 1.U
+
+    frame_info_update_en := true.B
+    slave_type_num       := Cat( "b00".U(2.W), slvNum )
+    slave_data_length    := ((8/8)*16-1).U
+
+    tx_start := false.B
+  } .elsewhen( stateCur === 1.U ){ // tx start
+    stateCur := 2.U
+
+    frame_info_update_en := false.B
+    tx_start := true.B
+
+  } .elsewhen( stateCur === 2.U ){
+
+    tx_start := false.B
+
+    when( lvdsMst.io.slave_link_num_valid ){
+      slvNum := lvdsMst.io.slave_link_num(5,0)
+      stateCur := 3.U
+    }
+
+  } .elsewhen( stateCur === 3.U ){
+    frame_info_update_en := false.B
+    slave_type_num       := 0.U
+    slave_data_length    := 0.U
+
+    tx_start := false.B
+
+    stateCur := 4.U
+    
+  } .elsewhen( stateCur === 4.U ){
+    stateCur := 5.U
+
+    frame_info_update_en := true.B
+    slave_type_num       := Cat( "b00".U(2.W), slvNum )
+    slave_data_length    := ((8/8)*16-1).U
+
+    tx_start := false.B
+  } .elsewhen( stateCur === 5.U ){ // tx start
+    stateCur := 6.U
+
+    frame_info_update_en := false.B
+    tx_start := true.B
+
+  } .elsewhen( stateCur === 6.U ){
+
+    tx_start := false.B
+
+    when( lvdsMst.io.slave_link_num_valid ){
+      when( slvNum === lvdsMst.io.slave_link_num(5,0) ){
+        stateCur := 7.U
+      } .otherwise{
+        printf("Initialization failed, waitting for timeout!\n")
+      }
+    }
+
+  } .elsewhen( stateCur === 7.U ){
+    when( ctrlSynch ){
+      stateCur := 8.U
+      synchCnt := 0.U
+    } .otherwise{
+      statusInit  := true.B
+      ctrlInit    := false.B
+    }
+
+  } .elsewhen( stateCur === 8.U ){   //synch
+    frame_info_update_en := false.B
+    slave_type_num       := 0.U
+    slave_data_length    := 0.U
+
+    tx_start := false.B
+
+    stateCur := 9.U
+    
+  } .elsewhen( stateCur === 9.U ){
+    stateCur := 10.U
+
+    frame_info_update_en := true.B
+    slave_type_num       := Cat( "b01".U(2.W), slvNum )
+    slave_data_length    := ((8/8)*16-1).U
+
+    tx_start := false.B
+  } .elsewhen( stateCur === 10.U ){ // tx start
+    stateCur := 11.U
+
+    frame_info_update_en := false.B
+    tx_start := true.B
+
+  } .elsewhen( stateCur === 11.U ){
+
+    tx_start := false.B
+
+    when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){
+      stateCur := 12.U
+      synchCnt := synchCnt + 1.U
+    }
+
+  } .elsewhen( stateCur === 12.U ){
+    when( synchCnt === 4.U ){
+      stateCur := 13.U
+    } .otherwise{
+      stateCur := 8.U
+    }
+  } .elsewhen( stateCur === 12.U ){
+    statusSynch := true.B
+    statusInit  := true.B
+    ctrlSynch   := false.B
+    ctrlInit    := false.B
+
+  } .elsewhen( stateCur === 15.U ){
+
+  }
+  .otherwise{
+    assert(false.B)
+  }
+
+
+}
+
+
+trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
+
+
+
+  val ( _, trigger ) = Counter(Range( 0,1000), ctrlTransmit )
 
 
   when( trigger ){  //reset
@@ -157,15 +350,12 @@ trait BackBoardMstLVDS{ this: BackBoardMstBase =>
 
     tx_start := false.B
     
-      isSync := ~isSync
 
   } .elsewhen( stateCur === 0.U  ){ //setting
     stateCur := 1.U
 
-
-
     frame_info_update_en := true.B
-      slave_type_num       := Mux(isSync, Cat( "b000".U(3.W), slvNum ), Cat( "b100".U(3.W), slvNum ) )
+    slave_type_num       := Cat( "b10".U(2.W), slvNum )
     slave_data_length    := ((8/8)*16-1).U
 
     tx_start := false.B
@@ -190,43 +380,53 @@ trait BackBoardMstLVDS{ this: BackBoardMstBase =>
     assert(false.B)
   }
 
-
-
-
-
-
-
-
   val addrr = RegInit(0.U(10.W))
   val addrw = RegInit(0.U(10.W))
 
-    when( trigger_wire ){
+  when( trigger ){
     addrw := 0.U
   } .elsewhen( lvdsMst.io.rx_data_valid & ~isSync){
-      assert( (stateCur_wire === 2.U) || (stateCur_wire === 3.U) )
+    assert( (stateCur === 2.U) || (stateCur === 3.U) )
     addrw := addrw + 1.U
   }
 
-    when( trigger_wire ){
+  when( trigger ){
     addrr := 0.U
   } .elsewhen( lvdsMst.io.tx_data_ready & ~isSync){
     addrr := addrr + 1.U
   }
 
-    mirrorDown.io.enr := (stateCur_wire === 1.U || stateCur_wire === 2.U) & ~isSync
+  mirrorDown.io.enr := (stateCur === 1.U || stateCur === 2.U) & ~isSync
   lvdsMst.io.tx_data_in := mirrorDown.io.datar
   mirrorDown.io.addrr := addrr
   
   mirrorUp.io.enw    := lvdsMst.io.rx_data_valid & ~isSync
   mirrorUp.io.dataw := lvdsMst.io.rx_data_out
   mirrorUp.io.addrw := addrw
-  }
-
-
-
-
-
 
 }
 
-class BackBoardMst extends BackBoardMstBase with BackBoardMstFSMC with BackBoardMstLVDS
+trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase =>
+  when( lvdsMst.io.closed_loop_err ){
+    slvOffLine    := lvdsMst.io.link_err_location(5,0)
+    statuslinkErr := true.B
+    statusSynch   := false.B
+    statusInit    := false.B
+  }
+
+  when( lvdsMst.io.upstream_cdr_err ){
+    statusCDRErr := true.B
+    ctrlTransmit := false.B
+  }
+
+  when( lvdsMst.io.upstream_crc_valid & upstream_crc_err ){
+    statusCRCErr := true.B
+    ctrlTransmit := false.B
+  }
+
+}
+
+class BackBoardMst extends BackBoardMstLVDSBase
+with BackBoardMstLVDSInitialization
+with BackBoardMstLVDSTransmit
+with BackBoardMstLVDSError

src/main/scala/backBoard/BackBoardSlv.scala

@@ -6,7 +6,8 @@ import chisel3.util._
 
 
 class BackBoardSlvIO extends Bundle{
-  val reset     = Input(Bool())
+
+  val reset_calib = Input(Bool())
   val oser_pclk = Input(Bool())
   val oser_fclk = Input(Bool())
   val ides_pclk = Input(Bool())
@@ -19,12 +20,13 @@ class BackBoardSlvIO extends Bundle{
 }
 
 
-abstract class BackBoardSlvBase extends RawModule{
+abstract class BackBoardSlvBase extends Module{
   val io: BackBoardSlvIO = IO(new BackBoardSlvIO)
 
   val lvdsSlv = Module(new Lvds_Bus_Slave)
 
-  lvdsSlv.io.rst_n     := ~io.reset    
+  lvdsSlv.io.rst_n       := ~reset.asBool()
+  lvdsSlv.io.reset_calib := io.reset_calib   
   lvdsSlv.io.oser_pclk   := io.oser_pclk
   lvdsSlv.io.oser_fclk   := io.oser_fclk
   lvdsSlv.io.ides_pclk   := io.ides_pclk
@@ -36,53 +38,33 @@ abstract class BackBoardSlvBase extends RawModule{
   lvdsSlv.io.lvds_up_din    := io.lvds_up_din   
   io.lvds_up_dout   := lvdsSlv.io.lvds_up_dout
 
-  val downRegWire = Wire(Vec(16, UInt(8.W)))
+  val downRegTemp = RegInit(VecInit(Seq.fill(16){0.U(8.W)}))
-  val upRegWire   = Wire(Vec(16, UInt(8.W)))
+  val downReg     = RegInit(VecInit(Seq.fill(16){0.U(8.W)}))
-
+  val upReg       = RegInit(VecInit((0 until 16).map{i => i.U(8.W)}))
-
-
-
-  // val downstream_rx_data_valid = Output(Bool())
-  // val downstream_rx_data_out   = Output(UInt(8.W))
-  // val downstream_rx_crc_valid  = Output(Bool())
-  // val downstream_rx_crc_err = Output(Bool())
-  // val downstream_rx_crc_err_counter = Output(UInt(8.W))
-  // val downstream_rx_cdr_err = Output(Bool())
-  // val downstream_sync = Output(Bool())
-
-  // val upstream_tx_data_ready = Output(Bool())
-  // val upstream_tx_data_in = Input(UInt(8.W))
-
-  // val upstream_rx_crc_valid = Output(Bool())
-  // val upstream_rx_crc_err = Output(Bool())
-  // val upstream_rx_crc_err_counter = Output(UInt(8.W))
-  // val upstream_rx_cdr_err = Output(Bool())
 }
 
 
 trait BackBoardSlvDown{ this: BackBoardSlvBase =>
 
-  withClockAndReset( io.oser_pclk.asClock, io.reset ){
-
-    val downReg = Reg(Vec(16, UInt(8.W))); downRegWire := downReg
-
 
   val downCnt = RegInit(0.U(6.W))
   val downTimeoutEn  = RegInit( false.B )
   val downTimeoutRst = (downCnt === 0.U & lvdsSlv.io.downstream_rx_data_valid)
-    val ( _, downTimeout ) = Counter( Range( 0,1023 ), downTimeoutEn, downTimeoutRst )
+  val ( _, downTimeout ) = Counter( Range( 0,1000 ), downTimeoutEn, downTimeoutRst )
+
 
 
-    when( io.reset ){
-      for( i <- 0 until 16 ){
-        downReg(i) := 0.U
-      }
-    } .otherwise{
   when( lvdsSlv.io.downstream_rx_data_valid ){
-        downReg(downCnt) := lvdsSlv.io.downstream_rx_data_out
+    downRegTemp(downCnt) := lvdsSlv.io.downstream_rx_data_out
+  }
+
+  when( lvdsSlv.io.downstream_rx_crc_valid ){
+    when( ~downstream_rx_crc_err ){
+      downReg := downRegTemp
     }
   }
 
+
   when( downTimeout ){
     downTimeoutEn := false.B
   } .elsewhen( downCnt === 16.U ){
@@ -99,22 +81,19 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
     downCnt := downCnt + 1.U
   }
 
-  }
+
 }
 
 trait BackBoardSlvUp{ this: BackBoardSlvBase =>
 
-  withClockAndReset( io.oser_pclk.asClock, io.reset ){
   val upCnt = RegInit(31.U(6.W))
   val upTimeoutEn  = RegInit( false.B )
   val upTimeoutRst = (upCnt === 0.U & lvdsSlv.io.upstream_tx_data_ready)
-    val ( _, upTimeout ) = Counter( Range( 0,1023 ), upTimeoutEn, upTimeoutRst )
+  val ( _, upTimeout ) = Counter( Range( 0,1000 ), upTimeoutEn, upTimeoutRst )
 
 
-    lvdsSlv.io.upstream_tx_data_in := upRegWire(upCnt)
+  lvdsSlv.io.upstream_tx_data_in := upReg(upCnt)
-      // when( upstream_tx_data_ready ){
+
-      //   upstream_tx_data_ready := upRegWire(upCnt)
-      // }
 
 
   when( upTimeout ){
@@ -135,7 +114,6 @@ trait BackBoardSlvUp{ this: BackBoardSlvBase =>
     }
   }
 
-  }
 }
 
 

src/main/scala/backBoard/LocalRegisters.scala

@@ -9,19 +9,17 @@ class BackBoardSlvDigitalIO extends BackBoardSlvBase with BackBoardSlvDown with
   val out = IO(Output(UInt(32.W)))
   val oe  = IO(Output(UInt(32.W)))
 
-  withClockAndReset( io.ides_pclk.asClock, io.reset ){
-    // val upReg   = Reg(Vec(32, UInt(8.W)))
-    val upReg   = RegInit(VecInit((0 until 16).map{i => i.U(8.W)}))
-    upRegWire   := upReg
-    out := Cat( (0 until 4).map{i => downRegWire(i)}.reverse )
-    oe  := Cat( (4 until 8).map{i => downRegWire(i)}.reverse )
 
-    when( true.B ){
+
+  out := Cat( (0 until 4).map{i => downReg(i)}.reverse )
+  oe  := Cat( (4 until 8).map{i => downReg(i)}.reverse )
+
+
   for( i <- 0 until 4 ) {
     upReg(i) := in( i*8+7,8*i )
   }
-    }
+
-  }
+
 }
 
 

src/main/scala/backBoard/goWinBus.scala

@@ -13,6 +13,7 @@ class CRC_ERR_Bundle extends Bundle{
 
 class Lvds_Bus_MasterIO extends Bundle{
   val rst_n       = Input(Bool())
+val reset_calib = Input(Bool())
   val oser_pclk   = Input(Bool())
   val oser_fclk   = Input(Bool())
   val ides_pclk   = Input(Bool())
@@ -24,6 +25,10 @@ class Lvds_Bus_MasterIO extends Bundle{
   val frame_info_update_en = Input(Bool())
   val slave_type_num       = Input(UInt(8.W))
   val slave_data_length    = Input(UInt(8.W))
+
+val slave_link_num_valid = Output(Bool())
+val slave_link_num = Output(UInt(7.W))
+
   val tx_start             = Input(Bool())
   val tx_data_in           = Input(UInt(8.W))
   val tx_data_ready        = Output(Bool())
@@ -34,8 +39,18 @@ class Lvds_Bus_MasterIO extends Bundle{
   val upstream_crc_valid     = Output(Bool())
   val upstream_crc_err       = Output(Bool())
   val upstream_crc_err_count = Output(UInt(8.W))
+  
   val upstream_cdr_err       = Output(Bool())
 
+val closed_loop_err   = Output(Bool())
+val link_err_location = Output(UInt(7.W))
+
+val test_downstream_tx_en       = Output(Bool())
+val test_downstream_tx_8b_data  = Output(UInt(8.W))
+val test_downstream_tx_10b_data = Output(UInt(10.W))
+val test_upstream_rx_busy       = Output(Bool())
+val test_upstream_rx_10b_data   = Output(UInt(10.W))
+val test_upstream_rx_8b_data    = Output(UInt(8.W))
 }
 
 class Lvds_Bus_Master extends BlackBox with HasBlackBoxInline {
@@ -46,6 +61,7 @@ class Lvds_Bus_Master extends BlackBox with HasBlackBoxInline {
               """
   | module Lvds_Bus_Master(
   | input rst_n,
+  | input reset_calib,
   | input oser_pclk,
   | input oser_fclk,
   | input ides_pclk,
@@ -54,7 +70,11 @@ class Lvds_Bus_Master extends BlackBox with HasBlackBoxInline {
   | input lvds_up_din,
   | input frame_info_update_en,
   | input [7:0] slave_type_num,
-  | input [7:0]slave_data_length,
+  | input [7:0] slave_data_length,
+  |
+  | output slave_link_num_valid,
+  | output [6:0] slave_link_num,
+  |
   | input tx_start,
   | input [7:0] tx_data_in,
   | output tx_data_ready,
@@ -64,10 +84,22 @@ class Lvds_Bus_Master extends BlackBox with HasBlackBoxInline {
   | output upstream_crc_valid,
   | output upstream_crc_err,
   | output [7:0] upstream_crc_err_count,
-  | output upstream_cdr_err
+  | output upstream_cdr_err,
+  |
+  | output closed_loop_err(closed_loop_err),
+  | output [6:0] link_err_location(link_err_location),
+  |  
+  | output test_downstream_tx_en(test_downstream_tx_en),
+  | output [7:0] test_downstream_tx_8b_data(test_downstream_tx_8b_data),
+  | output [9:0] test_downstream_tx_10b_data(test_downstream_tx_10b_data),
+  | output test_upstream_rx_busy(test_upstream_rx_busy),
+  | output [9:0] test_upstream_rx_10b_data(test_upstream_rx_10b_data),
+  | output [7:0] test_upstream_rx_8b_data(test_upstream_rx_8b_data)
   | );
+  |
   | lvds_bus_master_top i_lvds_bus_master(
   |   .rst_n(rst_n), //input
+  |   .reset_calib(reset_calib), //input
   |   .oser_pclk(oser_pclk), //input 
   |   .oser_fclk(oser_fclk), //input  
   |   .ides_pclk(ides_pclk), //input
@@ -79,6 +111,10 @@ class Lvds_Bus_Master extends BlackBox with HasBlackBoxInline {
   |   .frame_info_update_en(frame_info_update_en), //input 
   |   .slave_type_num(slave_type_num), //input [7:0]     
   |   .slave_data_length(slave_data_length), //input [7:0]
+  |
+  |   .slave_link_num_valid(slave_link_num_valid), //output
+  |   .slave_link_num(slave_link_num), //output [6:0]
+  |
   |   .tx_start(tx_start), //input   
   |   .tx_data_in(tx_data_in), //input [7:0]  
   |   .tx_data_ready(tx_data_ready), //output
@@ -89,13 +125,38 @@ class Lvds_Bus_Master extends BlackBox with HasBlackBoxInline {
   |   .upstream_crc_err(upstream_crc_err), //output
   |   .upstream_crc_err_count(upstream_crc_err_count), //output [7:0]
   |   .upstream_cdr_err(upstream_cdr_err) //output 
+  |
+  |   .closed_loop_err(closed_loop_err), //output
+  |   .link_err_location(link_err_location), //output [6:0]
+  |
+  |   .test_downstream_tx_en(test_downstream_tx_en), //output  
+  |   .test_downstream_tx_8b_data(test_downstream_tx_8b_data), //output [7:0]
+  |   .test_downstream_tx_10b_data(test_downstream_tx_10b_data), //output [9:0]
+  |   .test_upstream_rx_busy(test_upstream_rx_busy), //output
+  |   .test_upstream_rx_10b_data(test_upstream_rx_10b_data), //output [9:0]
+  |   .test_upstream_rx_8b_data(test_upstream_rx_8b_data) //output [7:0]  
   | );
   |endmodule
     """.stripMargin)
 }
 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
 class Lvds_Bus_SlaveIO extends Bundle{
   val rst_n     = Input(Bool())
+val reset_calib = Input(Bool())
   val oser_pclk = Input(Bool())
   val oser_fclk = Input(Bool())
   val ides_pclk = Input(Bool())
@@ -122,6 +183,20 @@ class Lvds_Bus_SlaveIO extends Bundle{
   val upstream_rx_crc_err = Output(Bool())
   val upstream_rx_crc_err_counter = Output(UInt(8.W))
   val upstream_rx_cdr_err = Output(Bool())
+
+val local_slave_id = Output(UInt(7.W))
+val test_downstream_rx_10b_data = Output(UInt(10.W))
+val test_downstream_rx_8b_data = Output(UInt(8.W))
+val test_downstream_rx_state_machine = Output(UInt(4.W))
+val test_downstream_tx_en = Output(Bool())
+val test_downstream_tx_8b_data = Output(UInt(8.W))
+val test_downstream_tx_10b_data = Output(UInt(10.W))
+val test_upstream_rx_10b_data = Output(UInt(10.W))
+val test_upstream_rx_8b_data = Output(UInt(8.W))
+val test_upstream_rx_state_machine = Output(UInt(4.W))
+val test_upstream_tx_en = Output(Bool())
+val test_upstream_tx_8b_data = Output(UInt(8.W))
+val test_upstream_tx_10b_data = Output(UInt(10.W))
 }
 
 
@@ -133,6 +208,7 @@ class Lvds_Bus_Slave extends BlackBox with HasBlackBoxInline {
               """
   module Lvds_Bus_Slave(
   |  input rst_n,
+  |  input reset_calib,
   |  input oser_pclk,
   |  input oser_fclk,
   |  input ides_pclk,
@@ -155,11 +231,26 @@ class Lvds_Bus_Slave extends BlackBox with HasBlackBoxInline {
   |  output upstream_rx_crc_valid,
   |  output upstream_rx_crc_err,
   |  output [7:0] upstream_rx_crc_err_counter,
-  |  output upstream_rx_cdr_err
+  |  output upstream_rx_cdr_err,
+  |
+  |  output [6:0] local_slave_id(local_slave_id),
+  |  output [9:0] test_downstream_rx_10b_data(test_downstream_rx_10b_data),
+  |  output [7:0] test_downstream_rx_8b_data(test_downstream_rx_8b_data),
+  |  output [3:0] test_downstream_rx_state_machine(test_downstream_rx_state_machine),
+  |  output test_downstream_tx_en(test_downstream_tx_en),
+  |  output [7:0] test_downstream_tx_8b_data(test_downstream_tx_8b_data),
+  |  output [9:0] test_downstream_tx_10b_data(test_downstream_tx_10b_data),
+  |  output [9:0] test_upstream_rx_10b_data(test_upstream_rx_10b_data),
+  |  output [7:0] test_upstream_rx_8b_data(test_upstream_rx_8b_data),
+  |  output [3:0] test_upstream_rx_state_machine(test_upstream_rx_state_machine),
+  |  output test_upstream_tx_en(test_upstream_tx_en),
+  |  output [7:0] test_upstream_tx_8b_data(test_upstream_tx_8b_data),
+  |  output [9:0] test_upstream_tx_10b_data(test_upstream_tx_10b_data)
   |);
   |
   |  lvds_bus_slave_top i_lvds_bus_slave(
   |  .rst_n(rst_n),
+  |  .reset_calib(reset_calib),
   |  .oser_pclk(oser_pclk),
   |  .oser_fclk(oser_fclk),
   |  .ides_pclk(ides_pclk),
@@ -182,9 +273,28 @@ class Lvds_Bus_Slave extends BlackBox with HasBlackBoxInline {
   |  .upstream_rx_crc_valid(upstream_rx_crc_valid),
   |  .upstream_rx_crc_err(upstream_rx_crc_err),
   |  .upstream_rx_crc_err_counter(upstream_rx_crc_err_counter),
-  |  .upstream_rx_cdr_err(upstream_rx_cdr_err)
+  |  .upstream_rx_cdr_err(upstream_rx_cdr_err),
+  |
+  |  .local_slave_id(local_slave_id), //output[6:0]
+  |  .test_downstream_rx_10b_data(test_downstream_rx_10b_data), //output[9:0]
+  |  .test_downstream_rx_8b_data(test_downstream_rx_8b_data), //output[7:0]
+  |  .test_downstream_rx_state_machine(test_downstream_rx_state_machine), //output[3:0]
+  |  .test_downstream_tx_en(test_downstream_tx_en), //output
+  |  .test_downstream_tx_8b_data(test_downstream_tx_8b_data), //output[7:0]
+  |  .test_downstream_tx_10b_data(test_downstream_tx_10b_data), //output[9:0]
+  |  .test_upstream_rx_10b_data(test_upstream_rx_10b_data), //output[9:0]
+  |  .test_upstream_rx_8b_data(test_upstream_rx_8b_data), //output[7:0]  
+  |  .test_upstream_rx_state_machine(test_upstream_rx_state_machine), //output[3:0]
+  |  .test_upstream_tx_en(test_upstream_tx_en), //output
+  |  .test_upstream_tx_8b_data(test_upstream_tx_8b_data), //output[7:0]
+  |  .test_upstream_tx_10b_data(test_upstream_tx_10b_data) //output[9:0]  
   |  );
   |endmodule
     """.stripMargin)
 }
 
+
+  //Test Signal// 
+
+
+

src/main/verilog/backBoardMstTop.v

@@ -35,7 +35,7 @@ wire       lvds_up_din;
 
 reg        rstn_d;
 
-
+wire lock;
 
 
 
@@ -45,9 +45,26 @@ always@(posedge clk_10m) begin
 	rst_n <= rstn_d;
 end
 
+//reset sync module, all the IDES/OSER and related CLKDIV MUST be reset by this module
+oser_rst u_oser_rst(
+  .clk_in(clock), // or any other speed comparble with fabric, DO NOT use HCLK as fabric cannot work at so high speed.
+  .rst_n(rst_n),
+  .pll_lock(lock), // trigged by PLL Lock
+  .reset_stop(reset_stop), // for DHCEN CE
+  .reset_calib(reset_calib), // for IDES and CLKDIV reset
+  .set_calib(), 
+  .ready()
+);
+
+DHCEN dhcen_inst (
+  .CLKIN(clk_400m),
+  .CE(reset_stop),
+  .CLKOUT(clk_400m_a)
+);
+
 
 Gowin_PLLO Gowin_PLLO(
-    .lock(),
+    .lock(lock),
     .clkouta(clk_400m),
     .clkoutc(clk_50m),
     .clkoutd(clk_100m),