new version

src/main/verilog/backBoardMstTop.v

@@ -35,19 +35,36 @@ wire       lvds_up_din;
 
 reg        rstn_d;
 
-
+wire lock;
 
 
 
 
 always@(posedge clk_10m) begin
-    rstn_d <= resetn;
+  rstn_d <= resetn;
 	rst_n <= rstn_d;
 end
 
+//reset sync module, all the IDES/OSER and related CLKDIV MUST be reset by this module
+oser_rst u_oser_rst(
+  .clk_in(clock), // or any other speed comparble with fabric, DO NOT use HCLK as fabric cannot work at so high speed.
+  .rst_n(rst_n),
+  .pll_lock(lock), // trigged by PLL Lock
+  .reset_stop(reset_stop), // for DHCEN CE
+  .reset_calib(reset_calib), // for IDES and CLKDIV reset
+  .set_calib(), 
+  .ready()
+);
+
+DHCEN dhcen_inst (
+  .CLKIN(clk_400m),
+  .CE(reset_stop),
+  .CLKOUT(clk_400m_a)
+);
+
 
 Gowin_PLLO Gowin_PLLO(
-    .lock(),
+    .lock(lock),
     .clkouta(clk_400m),
     .clkoutc(clk_50m),
     .clkoutd(clk_100m),