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This commit is contained in:
RuigeLee
2023-09-12 17:51:32 +08:00
parent 527f6bd761
commit 6fd836fc9c
5 changed files with 549 additions and 246 deletions
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128
src/main/scala/backBoard/goWinBus.scala
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@@ -12,11 +12,12 @@ class CRC_ERR_Bundle extends Bundle{
}
class Lvds_Bus_MasterIO extends Bundle{
val rst_n = Input(Bool())
val oser_pclk = Input(Bool())
val oser_fclk = Input(Bool())
val ides_pclk = Input(Bool())
val ides_fclk = Input(Bool())
val rst_n = Input(Bool())
val reset_calib = Input(Bool())
val oser_pclk = Input(Bool())
val oser_fclk = Input(Bool())
val ides_pclk = Input(Bool())
val ides_fclk = Input(Bool())
val lvds_down_dout = Output(Bool())
val lvds_up_din = Input(Bool())
@@ -24,6 +25,10 @@ class Lvds_Bus_MasterIO extends Bundle{
val frame_info_update_en = Input(Bool())
val slave_type_num = Input(UInt(8.W))
val slave_data_length = Input(UInt(8.W))
val slave_link_num_valid = Output(Bool())
val slave_link_num = Output(UInt(7.W))
val tx_start = Input(Bool())
val tx_data_in = Input(UInt(8.W))
val tx_data_ready = Output(Bool())
@@ -34,8 +39,18 @@ class Lvds_Bus_MasterIO extends Bundle{
val upstream_crc_valid = Output(Bool())
val upstream_crc_err = Output(Bool())
val upstream_crc_err_count = Output(UInt(8.W))
val upstream_cdr_err = Output(Bool())
val closed_loop_err = Output(Bool())
val link_err_location = Output(UInt(7.W))
val test_downstream_tx_en = Output(Bool())
val test_downstream_tx_8b_data = Output(UInt(8.W))
val test_downstream_tx_10b_data = Output(UInt(10.W))
val test_upstream_rx_busy = Output(Bool())
val test_upstream_rx_10b_data = Output(UInt(10.W))
val test_upstream_rx_8b_data = Output(UInt(8.W))
}
class Lvds_Bus_Master extends BlackBox with HasBlackBoxInline {
@@ -46,6 +61,7 @@ class Lvds_Bus_Master extends BlackBox with HasBlackBoxInline {
"""
| module Lvds_Bus_Master(
| input rst_n,
| input reset_calib,
| input oser_pclk,
| input oser_fclk,
| input ides_pclk,
@@ -54,7 +70,11 @@ class Lvds_Bus_Master extends BlackBox with HasBlackBoxInline {
| input lvds_up_din,
| input frame_info_update_en,
| input [7:0] slave_type_num,
| input [7:0]slave_data_length,
| input [7:0] slave_data_length,
|
| output slave_link_num_valid,
| output [6:0] slave_link_num,
|
| input tx_start,
| input [7:0] tx_data_in,
| output tx_data_ready,
@@ -64,10 +84,22 @@ class Lvds_Bus_Master extends BlackBox with HasBlackBoxInline {
| output upstream_crc_valid,
| output upstream_crc_err,
| output [7:0] upstream_crc_err_count,
| output upstream_cdr_err
| output upstream_cdr_err,
|
| output closed_loop_err(closed_loop_err),
| output [6:0] link_err_location(link_err_location),
|
| output test_downstream_tx_en(test_downstream_tx_en),
| output [7:0] test_downstream_tx_8b_data(test_downstream_tx_8b_data),
| output [9:0] test_downstream_tx_10b_data(test_downstream_tx_10b_data),
| output test_upstream_rx_busy(test_upstream_rx_busy),
| output [9:0] test_upstream_rx_10b_data(test_upstream_rx_10b_data),
| output [7:0] test_upstream_rx_8b_data(test_upstream_rx_8b_data)
| );
|
| lvds_bus_master_top i_lvds_bus_master(
| .rst_n(rst_n), //input
| .reset_calib(reset_calib), //input
| .oser_pclk(oser_pclk), //input
| .oser_fclk(oser_fclk), //input
| .ides_pclk(ides_pclk), //input
@@ -79,6 +111,10 @@ class Lvds_Bus_Master extends BlackBox with HasBlackBoxInline {
| .frame_info_update_en(frame_info_update_en), //input
| .slave_type_num(slave_type_num), //input [7:0]
| .slave_data_length(slave_data_length), //input [7:0]
|
| .slave_link_num_valid(slave_link_num_valid), //output
| .slave_link_num(slave_link_num), //output [6:0]
|
| .tx_start(tx_start), //input
| .tx_data_in(tx_data_in), //input [7:0]
| .tx_data_ready(tx_data_ready), //output
@@ -89,13 +125,38 @@ class Lvds_Bus_Master extends BlackBox with HasBlackBoxInline {
| .upstream_crc_err(upstream_crc_err), //output
| .upstream_crc_err_count(upstream_crc_err_count), //output [7:0]
| .upstream_cdr_err(upstream_cdr_err) //output
|
| .closed_loop_err(closed_loop_err), //output
| .link_err_location(link_err_location), //output [6:0]
|
| .test_downstream_tx_en(test_downstream_tx_en), //output
| .test_downstream_tx_8b_data(test_downstream_tx_8b_data), //output [7:0]
| .test_downstream_tx_10b_data(test_downstream_tx_10b_data), //output [9:0]
| .test_upstream_rx_busy(test_upstream_rx_busy), //output
| .test_upstream_rx_10b_data(test_upstream_rx_10b_data), //output [9:0]
| .test_upstream_rx_8b_data(test_upstream_rx_8b_data) //output [7:0]
| );
|endmodule
""".stripMargin)
}
class Lvds_Bus_SlaveIO extends Bundle{
val rst_n = Input(Bool())
val reset_calib = Input(Bool())
val oser_pclk = Input(Bool())
val oser_fclk = Input(Bool())
val ides_pclk = Input(Bool())
@@ -122,6 +183,20 @@ class Lvds_Bus_SlaveIO extends Bundle{
val upstream_rx_crc_err = Output(Bool())
val upstream_rx_crc_err_counter = Output(UInt(8.W))
val upstream_rx_cdr_err = Output(Bool())
val local_slave_id = Output(UInt(7.W))
val test_downstream_rx_10b_data = Output(UInt(10.W))
val test_downstream_rx_8b_data = Output(UInt(8.W))
val test_downstream_rx_state_machine = Output(UInt(4.W))
val test_downstream_tx_en = Output(Bool())
val test_downstream_tx_8b_data = Output(UInt(8.W))
val test_downstream_tx_10b_data = Output(UInt(10.W))
val test_upstream_rx_10b_data = Output(UInt(10.W))
val test_upstream_rx_8b_data = Output(UInt(8.W))
val test_upstream_rx_state_machine = Output(UInt(4.W))
val test_upstream_tx_en = Output(Bool())
val test_upstream_tx_8b_data = Output(UInt(8.W))
val test_upstream_tx_10b_data = Output(UInt(10.W))
}
@@ -133,6 +208,7 @@ class Lvds_Bus_Slave extends BlackBox with HasBlackBoxInline {
"""
module Lvds_Bus_Slave(
| input rst_n,
| input reset_calib,
| input oser_pclk,
| input oser_fclk,
| input ides_pclk,
@@ -155,11 +231,26 @@ class Lvds_Bus_Slave extends BlackBox with HasBlackBoxInline {
| output upstream_rx_crc_valid,
| output upstream_rx_crc_err,
| output [7:0] upstream_rx_crc_err_counter,
| output upstream_rx_cdr_err
| output upstream_rx_cdr_err,
|
| output [6:0] local_slave_id(local_slave_id),
| output [9:0] test_downstream_rx_10b_data(test_downstream_rx_10b_data),
| output [7:0] test_downstream_rx_8b_data(test_downstream_rx_8b_data),
| output [3:0] test_downstream_rx_state_machine(test_downstream_rx_state_machine),
| output test_downstream_tx_en(test_downstream_tx_en),
| output [7:0] test_downstream_tx_8b_data(test_downstream_tx_8b_data),
| output [9:0] test_downstream_tx_10b_data(test_downstream_tx_10b_data),
| output [9:0] test_upstream_rx_10b_data(test_upstream_rx_10b_data),
| output [7:0] test_upstream_rx_8b_data(test_upstream_rx_8b_data),
| output [3:0] test_upstream_rx_state_machine(test_upstream_rx_state_machine),
| output test_upstream_tx_en(test_upstream_tx_en),
| output [7:0] test_upstream_tx_8b_data(test_upstream_tx_8b_data),
| output [9:0] test_upstream_tx_10b_data(test_upstream_tx_10b_data)
|);
|
| lvds_bus_slave_top i_lvds_bus_slave(
| .rst_n(rst_n),
| .reset_calib(reset_calib),
| .oser_pclk(oser_pclk),
| .oser_fclk(oser_fclk),
| .ides_pclk(ides_pclk),
@@ -182,9 +273,28 @@ class Lvds_Bus_Slave extends BlackBox with HasBlackBoxInline {
| .upstream_rx_crc_valid(upstream_rx_crc_valid),
| .upstream_rx_crc_err(upstream_rx_crc_err),
| .upstream_rx_crc_err_counter(upstream_rx_crc_err_counter),
| .upstream_rx_cdr_err(upstream_rx_cdr_err)
| .upstream_rx_cdr_err(upstream_rx_cdr_err),
|
| .local_slave_id(local_slave_id), //output[6:0]
| .test_downstream_rx_10b_data(test_downstream_rx_10b_data), //output[9:0]
| .test_downstream_rx_8b_data(test_downstream_rx_8b_data), //output[7:0]
| .test_downstream_rx_state_machine(test_downstream_rx_state_machine), //output[3:0]
| .test_downstream_tx_en(test_downstream_tx_en), //output
| .test_downstream_tx_8b_data(test_downstream_tx_8b_data), //output[7:0]
| .test_downstream_tx_10b_data(test_downstream_tx_10b_data), //output[9:0]
| .test_upstream_rx_10b_data(test_upstream_rx_10b_data), //output[9:0]
| .test_upstream_rx_8b_data(test_upstream_rx_8b_data), //output[7:0]
| .test_upstream_rx_state_machine(test_upstream_rx_state_machine), //output[3:0]
| .test_upstream_tx_en(test_upstream_tx_en), //output
| .test_upstream_tx_8b_data(test_upstream_tx_8b_data), //output[7:0]
| .test_upstream_tx_10b_data(test_upstream_tx_10b_data) //output[9:0]
| );
|endmodule
""".stripMargin)
}
//Test Signal//