new version

src/main/scala/backBoard/LocalRegisters.scala

@@ -9,19 +9,17 @@ class BackBoardSlvDigitalIO extends BackBoardSlvBase with BackBoardSlvDown with
   val out = IO(Output(UInt(32.W)))
   val oe  = IO(Output(UInt(32.W)))
 
-  withClockAndReset( io.ides_pclk.asClock, io.reset ){
-    // val upReg   = Reg(Vec(32, UInt(8.W)))
-    val upReg   = RegInit(VecInit((0 until 16).map{i => i.U(8.W)}))
-    upRegWire   := upReg
-    out := Cat( (0 until 4).map{i => downRegWire(i)}.reverse )
-    oe  := Cat( (4 until 8).map{i => downRegWire(i)}.reverse )
 
-    when( true.B ){
-      for( i <- 0 until 4 ) {
-        upReg(i) := in( i*8+7,8*i )
-      }
-    }
+
+  out := Cat( (0 until 4).map{i => downReg(i)}.reverse )
+  oe  := Cat( (4 until 8).map{i => downReg(i)}.reverse )
+
+
+  for( i <- 0 until 4 ) {
+    upReg(i) := in( i*8+7,8*i )
   }
+
+
 }