new version

src/main/scala/backBoard/BackBoardSlv.scala

@@ -6,7 +6,8 @@ import chisel3.util._
 
 
 class BackBoardSlvIO extends Bundle{
-  val reset     = Input(Bool())
+
+  val reset_calib = Input(Bool())
   val oser_pclk = Input(Bool())
   val oser_fclk = Input(Bool())
   val ides_pclk = Input(Bool())
@@ -19,123 +20,100 @@ class BackBoardSlvIO extends Bundle{
 }
 
 
-abstract class BackBoardSlvBase extends RawModule{
+abstract class BackBoardSlvBase extends Module{
   val io: BackBoardSlvIO = IO(new BackBoardSlvIO)
 
   val lvdsSlv = Module(new Lvds_Bus_Slave)
 
-  lvdsSlv.io.rst_n     := ~io.reset    
-  lvdsSlv.io.oser_pclk := io.oser_pclk
-  lvdsSlv.io.oser_fclk := io.oser_fclk
-  lvdsSlv.io.ides_pclk := io.ides_pclk
-  lvdsSlv.io.ides_fclk := io.ides_fclk
+  lvdsSlv.io.rst_n       := ~reset.asBool()
+  lvdsSlv.io.reset_calib := io.reset_calib   
+  lvdsSlv.io.oser_pclk   := io.oser_pclk
+  lvdsSlv.io.oser_fclk   := io.oser_fclk
+  lvdsSlv.io.ides_pclk   := io.ides_pclk
+  lvdsSlv.io.ides_fclk   := io.ides_fclk
   
 
   lvdsSlv.io.lvds_down_din  := io.lvds_down_din 
   io.lvds_down_dout := lvdsSlv.io.lvds_down_dout
   lvdsSlv.io.lvds_up_din    := io.lvds_up_din   
   io.lvds_up_dout   := lvdsSlv.io.lvds_up_dout
-    
-  val downRegWire = Wire(Vec(16, UInt(8.W)))
-  val upRegWire   = Wire(Vec(16, UInt(8.W)))
 
-
-
-
-  // val downstream_rx_data_valid = Output(Bool())
-  // val downstream_rx_data_out   = Output(UInt(8.W))
-  // val downstream_rx_crc_valid  = Output(Bool())
-  // val downstream_rx_crc_err = Output(Bool())
-  // val downstream_rx_crc_err_counter = Output(UInt(8.W))
-  // val downstream_rx_cdr_err = Output(Bool())
-  // val downstream_sync = Output(Bool())
-
-  // val upstream_tx_data_ready = Output(Bool())
-  // val upstream_tx_data_in = Input(UInt(8.W))
-
-  // val upstream_rx_crc_valid = Output(Bool())
-  // val upstream_rx_crc_err = Output(Bool())
-  // val upstream_rx_crc_err_counter = Output(UInt(8.W))
-  // val upstream_rx_cdr_err = Output(Bool())
+  val downRegTemp = RegInit(VecInit(Seq.fill(16){0.U(8.W)}))
+  val downReg     = RegInit(VecInit(Seq.fill(16){0.U(8.W)}))
+  val upReg       = RegInit(VecInit((0 until 16).map{i => i.U(8.W)}))
 }
 
 
 trait BackBoardSlvDown{ this: BackBoardSlvBase =>
 
-  withClockAndReset( io.oser_pclk.asClock, io.reset ){
 
-    val downReg = Reg(Vec(16, UInt(8.W))); downRegWire := downReg
+  val downCnt = RegInit(0.U(6.W))
+  val downTimeoutEn  = RegInit( false.B )
+  val downTimeoutRst = (downCnt === 0.U & lvdsSlv.io.downstream_rx_data_valid)
+  val ( _, downTimeout ) = Counter( Range( 0,1000 ), downTimeoutEn, downTimeoutRst )
 
 
-    val downCnt = RegInit(0.U(6.W))
-    val downTimeoutEn  = RegInit( false.B )
-    val downTimeoutRst = (downCnt === 0.U & lvdsSlv.io.downstream_rx_data_valid)
-    val ( _, downTimeout ) = Counter( Range( 0,1023 ), downTimeoutEn, downTimeoutRst )
-
-
-    when( io.reset ){
-      for( i <- 0 until 16 ){
-        downReg(i) := 0.U
-      }
-    } .otherwise{
-      when( lvdsSlv.io.downstream_rx_data_valid ){
-        downReg(downCnt) := lvdsSlv.io.downstream_rx_data_out
-      }
-    }
-
-    when( downTimeout ){
-      downTimeoutEn := false.B
-    } .elsewhen( downCnt === 16.U ){
-      downTimeoutEn := false.B
-    } .elsewhen(downCnt === 0.U & lvdsSlv.io.downstream_rx_data_valid){
-      downTimeoutEn := true.B
-    }
-
-    when( downTimeout ){
-      downCnt := 0.U
-    }.elsewhen( downCnt === 16.U ){
-      downCnt := 0.U
-    }.elsewhen( lvdsSlv.io.downstream_rx_data_valid ){
-      downCnt := downCnt + 1.U
-    }
 
+  when( lvdsSlv.io.downstream_rx_data_valid ){
+    downRegTemp(downCnt) := lvdsSlv.io.downstream_rx_data_out
   }
+
+  when( lvdsSlv.io.downstream_rx_crc_valid ){
+    when( ~downstream_rx_crc_err ){
+      downReg := downRegTemp
+    }
+  }
+
+
+  when( downTimeout ){
+    downTimeoutEn := false.B
+  } .elsewhen( downCnt === 16.U ){
+    downTimeoutEn := false.B
+  } .elsewhen(downCnt === 0.U & lvdsSlv.io.downstream_rx_data_valid){
+    downTimeoutEn := true.B
+  }
+
+  when( downTimeout ){
+    downCnt := 0.U
+  }.elsewhen( downCnt === 16.U ){
+    downCnt := 0.U
+  }.elsewhen( lvdsSlv.io.downstream_rx_data_valid ){
+    downCnt := downCnt + 1.U
+  }
+
+
 }
 
 trait BackBoardSlvUp{ this: BackBoardSlvBase =>
 
-  withClockAndReset( io.oser_pclk.asClock, io.reset ){
-    val upCnt = RegInit(31.U(6.W))
-    val upTimeoutEn  = RegInit( false.B )
-    val upTimeoutRst = (upCnt === 0.U & lvdsSlv.io.upstream_tx_data_ready)
-    val ( _, upTimeout ) = Counter( Range( 0,1023 ), upTimeoutEn, upTimeoutRst )
+  val upCnt = RegInit(31.U(6.W))
+  val upTimeoutEn  = RegInit( false.B )
+  val upTimeoutRst = (upCnt === 0.U & lvdsSlv.io.upstream_tx_data_ready)
+  val ( _, upTimeout ) = Counter( Range( 0,1000 ), upTimeoutEn, upTimeoutRst )
 
 
-    lvdsSlv.io.upstream_tx_data_in := upRegWire(upCnt)
-      // when( upstream_tx_data_ready ){
-      //   upstream_tx_data_ready := upRegWire(upCnt)
-      // }
+  lvdsSlv.io.upstream_tx_data_in := upReg(upCnt)
 
 
-    when( upTimeout ){
-      upTimeoutEn := false.B
-    } .elsewhen( upCnt === 31.U ){
-      upTimeoutEn := false.B
-    } .elsewhen(upCnt === 0.U & lvdsSlv.io.upstream_tx_data_ready){
-      upTimeoutEn := true.B
-    }
-
-    when( upTimeout ){
-      upCnt := 0.U
-    }.elsewhen( lvdsSlv.io.upstream_tx_data_ready ){
-      when(upCnt === 31.U){
-        upCnt := 0.U        
-      } .elsewhen( lvdsSlv.io.upstream_tx_data_ready ){
-        upCnt := upCnt + 1.U
-      }
-    }
 
+  when( upTimeout ){
+    upTimeoutEn := false.B
+  } .elsewhen( upCnt === 31.U ){
+    upTimeoutEn := false.B
+  } .elsewhen(upCnt === 0.U & lvdsSlv.io.upstream_tx_data_ready){
+    upTimeoutEn := true.B
   }
+
+  when( upTimeout ){
+    upCnt := 0.U
+  }.elsewhen( lvdsSlv.io.upstream_tx_data_ready ){
+    when(upCnt === 31.U){
+      upCnt := 0.U        
+    } .elsewhen( lvdsSlv.io.upstream_tx_data_ready ){
+      upCnt := upCnt + 1.U
+    }
+  }
+
 }