new version
This commit is contained in:
RuigeLee
@@ -21,7 +21,8 @@ class FSMC_Port_Bundle extends Bundle{
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class BackBoardMstIO extends Bundle{
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val FSMC = new FSMC_Port_Bundle
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val reset = Input(Bool())
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// val reset = Input(Bool())
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val reset_calib = Input(Bool())
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val oser_pclk = Input(Bool())
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val oser_fclk = Input(Bool())
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val ides_pclk = Input(Bool())
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@@ -29,27 +30,70 @@ class BackBoardMstIO extends Bundle{
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val lvds_down_dout = Output(Bool())
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val lvds_up_din = Input(Bool())
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val cdrErr = Output(Bool())
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val crcErr = Output(Bool())
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val linkErr = Output(Bool())
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}
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// class Master_Status_Bundle extends Bundle{
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// val zero = UInt(11.W)
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// val cdrErr = Bool()
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// val crcErr = Bool()
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// val linkErr = Bool()
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// val synchronize = Bool()
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// val initialization = Bool()
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// }
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class BackBoardMstBase extends RawModule{
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// class Master_Control_Bundle extends Bundle{
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// val zero = UInt(13.W)
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// val transmit = Bool()
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// val synchronize = Bool()
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// val initialization = Bool()
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// }
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class BackBoardMstBase extends Module{ //10M
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val io: BackBoardMstIO = IO(new BackBoardMstIO)
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val lvdsMst = Module(new Lvds_Bus_Master)
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val mirrorDown = Module(new MirrorSRAMDown())
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val mirrorUp = Module(new MirrorSRAMUp())
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val status = Wire(UInt(16.W))
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val slvNum = Wire(UInt(5.W))
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val statusCDRErr = RegInit( false.B )
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val statusCRCErr = RegInit( false.B )
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val statusLinkErr = RegInit( false.B )
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val statusSynch = RegInit( false.B )
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val statusInit = RegInit( false.B )
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val ctrlTransmit = RegInit( false.B )
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val ctrlCDRErr = RegInit( false.B )
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val ctrlCRCErr = RegInit( false.B )
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val ctrlLinkErr = RegInit( false.B )
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val ctrlSynch = RegInit( false.B )
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val ctrlInit = RegInit( false.B )
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val slvNum = RegInit(0.U(6.W))
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val slvOffLine = RegInit(0.U(6.W))
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lvdsMst.io.rst_n := ~reset.asBool
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lvdsMst.io.reset_calib := io.reset_calib
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lvdsMst.io.oser_pclk := io.oser_pclk
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lvdsMst.io.oser_fclk := io.oser_fclk
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lvdsMst.io.ides_pclk := io.ides_pclk
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lvdsMst.io.ides_fclk := io.ides_fclk
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io.lvds_down_dout := lvdsMst.io.lvds_down_dout
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lvdsMst.io.lvds_up_din := io.lvds_up_din
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mirrorDown.io.clockw := io.ides_pclk.asBool
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mirrorDown.io.clockw := io.oser_pclk.asBool
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mirrorDown.io.clockr := io.oser_pclk.asBool
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mirrorUp.io.clockw := io.oser_pclk.asBool
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mirrorUp.io.clockr := io.ides_pclk.asBool
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mirrorUp.io.clockr := io.oser_pclk.asBool
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}
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@@ -58,175 +102,331 @@ class BackBoardMstBase extends RawModule{
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trait BackBoardMstFSMC{ this: BackBoardMstBase =>
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withClockAndReset( io.ides_pclk.asClock, io.reset ){
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val statusReg = RegInit(0.U(16.W)); status := statusReg
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val slvNumReg = RegInit(1.U(5.W)); slvNum := slvNumReg
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val fsmcAddrSync = ShiftRegister( io.FSMC.addr, 2, 0.U, true.B )
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val fsmcdataInSync = ShiftRegister( io.FSMC.dataIn, 2, 0.U, true.B )
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val fsmcCEnSync = ShiftRegister( io.FSMC.cen, 2, true.B, true.B )
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val fsmcOEnSync = ShiftRegister( io.FSMC.oen, 2, true.B, true.B )
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val fsmcWEnSync = ShiftRegister( io.FSMC.wen, 2, true.B, true.B )
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io.FSMC.dataOEn := io.FSMC.oen
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val isAccessSRAM = ~fsmcAddrSync.extract(9)
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val isAccessReg = fsmcAddrSync.extract(9)
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val activeAddr = fsmcAddrSync(8,0)
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val regOut = Wire(UInt(16.W))
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val fsmcAddrSync = ShiftRegister( io.FSMC.addr, 2, 0.U, true.B )
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val fsmcdataInSync = ShiftRegister( io.FSMC.dataIn, 2, 0.U, true.B )
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val fsmcCEnSync = ShiftRegister( io.FSMC.cen, 2, true.B, true.B )
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val fsmcOEnSync = ShiftRegister( io.FSMC.oen, 2, true.B, true.B )
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val fsmcWEnSync = ShiftRegister( io.FSMC.wen, 2, true.B, true.B )
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io.FSMC.dataOEn := io.FSMC.oen
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val isAccessSRAM = ~fsmcAddrSync.extract(9)
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val isAccessReg = fsmcAddrSync.extract(9)
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val activeAddr = fsmcAddrSync(8,0)
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val regOut = Wire(UInt(16.W))
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mirrorDown.io.enw := (~fsmcCEnSync & isAccessSRAM & (~fsmcWEnSync) )
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mirrorDown.io.addrw := activeAddr
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mirrorDown.io.dataw := fsmcdataInSync
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mirrorDown.io.enw := (~fsmcCEnSync & isAccessSRAM & (~fsmcWEnSync) )
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mirrorDown.io.addrw := activeAddr
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mirrorDown.io.dataw := fsmcdataInSync
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mirrorUp.io.enr := (~fsmcCEnSync & isAccessSRAM & (~fsmcOEnSync) )
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mirrorUp.io.addrr := activeAddr
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mirrorUp.io.enr := (~fsmcCEnSync & isAccessSRAM & (~fsmcOEnSync) )
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mirrorUp.io.addrr := activeAddr
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io.FSMC.dataOut := Mux( isAccessReg, regOut, mirrorUp.io.datar)
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io.FSMC.dataOut := Mux( isAccessReg, regOut, mirrorUp.io.datar)
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regOut := Mux1H(Seq(
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( activeAddr === 0.U) -> status,
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( activeAddr === 1.U) -> slvNum,
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))
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regOut := Mux1H(Seq(
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( activeAddr === 0.U) ->
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Cat(
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statusCDRErr ,
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statusCRCErr ,
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statusLinkErr,
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statusSynch ,
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statusInit
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),
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( activeAddr === 1.U) ->
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Cat(
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ctrlTransmit,
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ctrlCDRErr ,
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ctrlCRCErr ,
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ctrlLinkErr ,
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ctrlSynch ,
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ctrlInit
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),
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( activeAddr === 2.U) -> slvNum,
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( activeAddr === 3.U) -> slvOffLine,
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))
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when( (~fsmcCEnSync & isAccessReg & (~fsmcWEnSync) ) & ( activeAddr === 0.U) ){
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statusReg := fsmcdataInSync
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}
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when( (~fsmcCEnSync & isAccessReg & (~fsmcWEnSync) ) & ( activeAddr === 1.U) ){
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slvNumReg := fsmcdataInSync
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}
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// when( (~fsmcCEnSync & isAccessReg & (~fsmcWEnSync) ) & ( activeAddr === 0.U) ){
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// status := fsmcdataInSync
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// }
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when( (~fsmcCEnSync & isAccessReg & (~fsmcWEnSync) ) & ( activeAddr === 1.U) ){
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ctrlTransmit := fsmcdataInSync.extract(5)
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ctrlCDRErr := fsmcdataInSync.extract(4)
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ctrlCRCErr := fsmcdataInSync.extract(3)
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ctrlLinkErr := fsmcdataInSync.extract(2)
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ctrlSynch := fsmcdataInSync.extract(1)
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ctrlInit := fsmcdataInSync.extract(0)
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}
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// when( (~fsmcCEnSync & isAccessReg & (~fsmcWEnSync) ) & ( activeAddr === 2.U) ){
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// slvNum := fsmcdataInSync
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// }
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when( (~fsmcCEnSync & isAccessReg & (~fsmcWEnSync) ) & ( activeAddr === 3.U) ){
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slvOffLine := fsmcdataInSync
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}
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}
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trait BackBoardMstLVDS{ this: BackBoardMstBase =>
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lvdsMst.io.rst_n := ~io.reset
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lvdsMst.io.oser_pclk := io.oser_pclk
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lvdsMst.io.oser_fclk := io.oser_fclk
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lvdsMst.io.ides_pclk := io.ides_pclk
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lvdsMst.io.ides_fclk := io.ides_fclk
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io.lvds_down_dout := lvdsMst.io.lvds_down_dout
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lvdsMst.io.lvds_up_din := io.lvds_up_din
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abstract class BackBoardMstLVDSBase extends BackBoardMstBase with BackBoardMstFSMC{
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val frame_info_update_en = RegInit(false.B)
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val slave_type_num = RegInit(0.U(8.W))
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val slave_data_length = RegInit(0.U(8.W))
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val tx_start = RegInit(false.B)
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lvdsMst.io.frame_info_update_en := frame_info_update_en
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lvdsMst.io.slave_type_num := slave_type_num
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lvdsMst.io.slave_data_length := slave_data_length
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lvdsMst.io.tx_start := tx_start
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val stateCur = RegInit(15.U(4.W))
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}
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trait BackBoardMstLVDSInitialization{ this: BackBoardMstLVDSBase =>
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val isInitCntReset = ( ~RegNext(ctrlInit) & ctrlInit ) | (stateCur === 3.U) | (stateCur === 8.U)
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val ( _, isInitTimeout ) = Counter(Range( 0,5200), ctrlInit, isInitCntReset)
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val synchCnt = Reg(UInt(3.W))
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when( isInitTimeout ){
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stateCur := 0.U
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frame_info_update_en := false.B
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slave_type_num := 0.U
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slave_data_length := 0.U
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tx_start := false.B
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lvdsMst.io.tx_start := false.B
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} .elsewhen( stateCur === 0.U ){
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stateCur := 1.U
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frame_info_update_en := true.B
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slave_type_num := Cat( "b00".U(2.W), slvNum )
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slave_data_length := ((8/8)*16-1).U
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val trigger_wire = Wire(Bool())
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val stateCur_wire = Wire( UInt(4.W) )
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tx_start := false.B
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} .elsewhen( stateCur === 1.U ){ // tx start
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stateCur := 2.U
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withClockAndReset( io.oser_pclk.asClock, io.reset ){
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frame_info_update_en := false.B
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tx_start := true.B
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val stateCur = RegInit(3.U(4.W))
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stateCur_wire := stateCur
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} .elsewhen( stateCur === 2.U ){
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tx_start := false.B
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val ( _, trigger ) = Counter(Range( 0,1000) )
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trigger_wire := trigger
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when( lvdsMst.io.slave_link_num_valid ){
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slvNum := lvdsMst.io.slave_link_num(5,0)
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stateCur := 3.U
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}
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val isSync = RegInit(false.B)
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} .elsewhen( stateCur === 3.U ){
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frame_info_update_en := false.B
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slave_type_num := 0.U
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slave_data_length := 0.U
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tx_start := false.B
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val frame_info_update_en = RegInit(false.B)
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stateCur := 4.U
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} .elsewhen( stateCur === 4.U ){
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stateCur := 5.U
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val slave_type_num = RegInit(0.U(8.W))
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val slave_data_length = RegInit(0.U(8.W))
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val tx_start = RegInit(false.B)
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frame_info_update_en := true.B
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slave_type_num := Cat( "b00".U(2.W), slvNum )
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slave_data_length := ((8/8)*16-1).U
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lvdsMst.io.frame_info_update_en := frame_info_update_en
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lvdsMst.io.slave_type_num := slave_type_num
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lvdsMst.io.slave_data_length := slave_data_length
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lvdsMst.io.tx_start := tx_start
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tx_start := false.B
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} .elsewhen( stateCur === 5.U ){ // tx start
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stateCur := 6.U
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frame_info_update_en := false.B
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tx_start := true.B
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} .elsewhen( stateCur === 6.U ){
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when( trigger ){ //reset
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stateCur := 0.U
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tx_start := false.B
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frame_info_update_en := false.B
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slave_type_num := 0.U
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slave_data_length := 0.U
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tx_start := false.B
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isSync := ~isSync
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} .elsewhen( stateCur === 0.U ){ //setting
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stateCur := 1.U
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frame_info_update_en := true.B
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slave_type_num := Mux(isSync, Cat( "b000".U(3.W), slvNum ), Cat( "b100".U(3.W), slvNum ) )
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slave_data_length := ((8/8)*16-1).U
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tx_start := false.B
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} .elsewhen( stateCur === 1.U ){ // tx start
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stateCur := 2.U
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frame_info_update_en := false.B
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tx_start := true.B
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} .elsewhen( stateCur === 2.U ){ //waiting for busy drop
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tx_start := false.B
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when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){
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stateCur := 3.U
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when( lvdsMst.io.slave_link_num_valid ){
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when( slvNum === lvdsMst.io.slave_link_num(5,0) ){
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stateCur := 7.U
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} .otherwise{
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printf("Initialization failed, waitting for timeout!\n")
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}
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}
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} .elsewhen( stateCur === 3.U ){
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} .elsewhen( stateCur === 7.U ){
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when( ctrlSynch ){
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stateCur := 8.U
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synchCnt := 0.U
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} .otherwise{
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assert(false.B)
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statusInit := true.B
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ctrlInit := false.B
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}
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} .elsewhen( stateCur === 8.U ){ //synch
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frame_info_update_en := false.B
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slave_type_num := 0.U
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slave_data_length := 0.U
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tx_start := false.B
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val addrr = RegInit(0.U(10.W))
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val addrw = RegInit(0.U(10.W))
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when( trigger_wire ){
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addrw := 0.U
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} .elsewhen( lvdsMst.io.rx_data_valid & ~isSync){
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assert( (stateCur_wire === 2.U) || (stateCur_wire === 3.U) )
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addrw := addrw + 1.U
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}
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when( trigger_wire ){
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addrr := 0.U
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} .elsewhen( lvdsMst.io.tx_data_ready & ~isSync){
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addrr := addrr + 1.U
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}
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mirrorDown.io.enr := (stateCur_wire === 1.U || stateCur_wire === 2.U) & ~isSync
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lvdsMst.io.tx_data_in := mirrorDown.io.datar
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mirrorDown.io.addrr := addrr
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stateCur := 9.U
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mirrorUp.io.enw := lvdsMst.io.rx_data_valid & ~isSync
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mirrorUp.io.dataw := lvdsMst.io.rx_data_out
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mirrorUp.io.addrw := addrw
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} .elsewhen( stateCur === 9.U ){
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stateCur := 10.U
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frame_info_update_en := true.B
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slave_type_num := Cat( "b01".U(2.W), slvNum )
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slave_data_length := ((8/8)*16-1).U
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tx_start := false.B
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} .elsewhen( stateCur === 10.U ){ // tx start
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stateCur := 11.U
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frame_info_update_en := false.B
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tx_start := true.B
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} .elsewhen( stateCur === 11.U ){
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tx_start := false.B
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when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){
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stateCur := 12.U
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synchCnt := synchCnt + 1.U
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}
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} .elsewhen( stateCur === 12.U ){
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when( synchCnt === 4.U ){
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stateCur := 13.U
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} .otherwise{
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stateCur := 8.U
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}
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} .elsewhen( stateCur === 12.U ){
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statusSynch := true.B
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statusInit := true.B
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ctrlSynch := false.B
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ctrlInit := false.B
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} .elsewhen( stateCur === 15.U ){
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}
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.otherwise{
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assert(false.B)
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}
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}
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class BackBoardMst extends BackBoardMstBase with BackBoardMstFSMC with BackBoardMstLVDS
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trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
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||||
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val ( _, trigger ) = Counter(Range( 0,1000), ctrlTransmit )
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when( trigger ){ //reset
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||||
stateCur := 0.U
|
||||
|
||||
frame_info_update_en := false.B
|
||||
slave_type_num := 0.U
|
||||
slave_data_length := 0.U
|
||||
|
||||
tx_start := false.B
|
||||
|
||||
|
||||
} .elsewhen( stateCur === 0.U ){ //setting
|
||||
stateCur := 1.U
|
||||
|
||||
frame_info_update_en := true.B
|
||||
slave_type_num := Cat( "b10".U(2.W), slvNum )
|
||||
slave_data_length := ((8/8)*16-1).U
|
||||
|
||||
tx_start := false.B
|
||||
} .elsewhen( stateCur === 1.U ){ // tx start
|
||||
stateCur := 2.U
|
||||
|
||||
frame_info_update_en := false.B
|
||||
tx_start := true.B
|
||||
|
||||
} .elsewhen( stateCur === 2.U ){ //waiting for busy drop
|
||||
|
||||
tx_start := false.B
|
||||
|
||||
when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){
|
||||
stateCur := 3.U
|
||||
}
|
||||
|
||||
} .elsewhen( stateCur === 3.U ){
|
||||
|
||||
} .otherwise{
|
||||
|
||||
assert(false.B)
|
||||
}
|
||||
|
||||
val addrr = RegInit(0.U(10.W))
|
||||
val addrw = RegInit(0.U(10.W))
|
||||
|
||||
when( trigger ){
|
||||
addrw := 0.U
|
||||
} .elsewhen( lvdsMst.io.rx_data_valid & ~isSync){
|
||||
assert( (stateCur === 2.U) || (stateCur === 3.U) )
|
||||
addrw := addrw + 1.U
|
||||
}
|
||||
|
||||
when( trigger ){
|
||||
addrr := 0.U
|
||||
} .elsewhen( lvdsMst.io.tx_data_ready & ~isSync){
|
||||
addrr := addrr + 1.U
|
||||
}
|
||||
|
||||
mirrorDown.io.enr := (stateCur === 1.U || stateCur === 2.U) & ~isSync
|
||||
lvdsMst.io.tx_data_in := mirrorDown.io.datar
|
||||
mirrorDown.io.addrr := addrr
|
||||
|
||||
mirrorUp.io.enw := lvdsMst.io.rx_data_valid & ~isSync
|
||||
mirrorUp.io.dataw := lvdsMst.io.rx_data_out
|
||||
mirrorUp.io.addrw := addrw
|
||||
|
||||
}
|
||||
|
||||
trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase =>
|
||||
when( lvdsMst.io.closed_loop_err ){
|
||||
slvOffLine := lvdsMst.io.link_err_location(5,0)
|
||||
statuslinkErr := true.B
|
||||
statusSynch := false.B
|
||||
statusInit := false.B
|
||||
}
|
||||
|
||||
when( lvdsMst.io.upstream_cdr_err ){
|
||||
statusCDRErr := true.B
|
||||
ctrlTransmit := false.B
|
||||
}
|
||||
|
||||
when( lvdsMst.io.upstream_crc_valid & upstream_crc_err ){
|
||||
statusCRCErr := true.B
|
||||
ctrlTransmit := false.B
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
class BackBoardMst extends BackBoardMstLVDSBase
|
||||
with BackBoardMstLVDSInitialization
|
||||
with BackBoardMstLVDSTransmit
|
||||
with BackBoardMstLVDSError
|
||||
|
||||
Reference in New Issue
Block a user