From 6fa2ef5f6efe39318c5789b19eb934683ea04b9d Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Wed, 16 Aug 2023 22:25:30 +0800 Subject: [PATCH] porta --- src/main/scala/backBoard/BackBoardMst.scala | 107 +++++++++++++------- src/main/scala/backBoard/FSMC.scala | 69 +++---------- src/main/scala/backBoard/MirrorSRAM.scala | 100 ++++++++++++++++++ 3 files changed, 185 insertions(+), 91 deletions(-) create mode 100644 src/main/scala/backBoard/MirrorSRAM.scala diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala index af0b64b..ee2a2db 100644 --- a/src/main/scala/backBoard/BackBoardMst.scala +++ b/src/main/scala/backBoard/BackBoardMst.scala @@ -3,6 +3,17 @@ package BACK import chisel3._ import chisel3.util._ +class FSMC_Port_Bundle extends Bundle{ + + val addr = Input(UInt(12.W)) + val dataIn = Input(UInt(8.W)) + val dataOut = Output(UInt(8.W)) + val dataOEn = Output(Bool()) + val cen = Input(Bool()) + val oen = Input(Bool()) + val wen = Input(Bool()) +} + class BackBoardMstIO extends Bundle{ val FSMC = new FSMC_Port_Bundle @@ -10,7 +21,7 @@ class BackBoardMstIO extends Bundle{ val reset = Input(Bool()) val oser_pclk = Input(Bool()) val oser_fclk = Input(Bool()) - val ides_pclk = Input(Bool()) + val ides_pclk = Input(Bool()) val ides_fclk = Input(Bool()) val lvds_down_dout = Output(Bool()) @@ -18,7 +29,7 @@ class BackBoardMstIO extends Bundle{ } -class BackBoardMst extends RawModule{ +class BackBoardMstBase extends Module{ val io: BackBoardMstIO = IO(new BackBoardMstIO) @@ -27,11 +38,50 @@ class BackBoardMst extends RawModule{ fsmcSlv.io.FSMC <> io.FSMC - - - - val lvdsMst = Module(new Lvds_Bus_Master) + + + + val ( cnt, trigger ) = Counter(Range( 0,1023)) + + + + + + + val status = RegInit(0.U(8.W)) + val slvNum = RegInit(0.U(6.W)) + + val mirror = Module(new MirrorSRAM) + mirror.io.clock := io.ides_pclk.asBool + mirror.io.reset := io.reset.asBool + +} + + + + + +trait BackBoardMstFSMC{ this: BackBoardMstBase => + + val fsmcAddrSync = ShiftRegister( io.FSMC.addr, 2, 0.U, true.B ) + val fsmcdataInSync = ShiftRegister( io.FSMC.dataIn, 2, 0.U, true.B ) + val fsmcCEnSync = ShiftRegister( io.FSMC.cen, 2, true.B, true.B ) + val fsmcOEnSync = ShiftRegister( io.FSMC.oen, 2, true.B, true.B ) + val fsmcWEnSync = ShiftRegister( io.FSMC.wen, 2, true.B, true.B ) + + io.FSMC.dataOEn := io.FSMC.oen + + + io.FSMC.dataOut := mirror.io.datar_a + mirror.io.ce_a := (~fsmcCEnSync & ~fsmcAddrSync.extract(11) & (~fsmcOEnSync | ~fsmcWEnSync) ) + mirror.io.we_a := ~fsmcWEnSync + mirror.io.addr_a := fsmcAddrSync(10,0) + mirror.io.dataw_a := fsmcdataInSync + +} + +trait BackBoardMstLVDS{ this: BackBoardMstBase => lvdsMst.io.rst_n := ~io.reset lvdsMst.io.oser_pclk := io.oser_pclk lvdsMst.io.oser_fclk := io.oser_fclk @@ -41,16 +91,27 @@ class BackBoardMst extends RawModule{ io.lvds_down_dout := lvdsMst.io.lvds_down_dout lvdsMst.io.lvds_up_din := io.lvds_up_din + + lvdsMst.io.tx_start := false.B + + + .elsewhen( cnt === 0.U ){ + + } .elsewhen( cnt === 1.U ){ + lvdsMst.io.tx_start := true.B + } + lvdsMst.io.frame_info_update_en := (cnt === 0.U) + lvdsMst.io.slave_type_num := Cat( "b00".U(2.W), slvNum ) + lvdsMst.io.slave_data_length := (8/8*4*8-1).U + - lvdsMst.io.frame_info_update_en = Input(Bool()) - lvdsMst.io.slave_type_num = Input(UInt(8.W)) - lvdsMst.io.slave_data_length = Input(UInt(8.W)) lvdsMst.io.tx_start = Input(Bool()) lvdsMst.io.tx_data_in = Input(UInt(8.W)) lvdsMst.io.tx_data_ready = Output(Bool()) lvdsMst.io.downstream_busy = Output(Bool()) + lvdsMst.io.rx_data_out = Output(UInt(8.W)) lvdsMst.io.rx_data_valid = Output(Bool()) @@ -58,30 +119,4 @@ class BackBoardMst extends RawModule{ lvdsMst.io.upstream_crc_err = Output(Bool()) lvdsMst.io.upstream_crc_err_count = Output(UInt(8.W)) lvdsMst.io.upstream_cdr_err = Output(Bool()) - - - - - fsmcSlv.io.CDRIn = Flipped(Valid(new CDRData)) - fsmcSlv.io.CDROut = Valid(new CDRData) - - - - val stateNxt = Wire( UInt( 2.W ) ) - val stateCur = RegNext( stateNxt, 0.U ) - - when( stateCur === 0.U ){ - stateNxt := 0.U - when( ) - } .elsewhen( stateCur === 1.U ){ - stateNxt := 1.U - } .elsewhen( stateCur === 2.U ){ - stateNxt := 2.U - } .elsewhen( stateCur === 3.U ){ - stateNxt := 3.U - } - - - - -} \ No newline at end of file +} diff --git a/src/main/scala/backBoard/FSMC.scala b/src/main/scala/backBoard/FSMC.scala index bb6fa74..04220af 100644 --- a/src/main/scala/backBoard/FSMC.scala +++ b/src/main/scala/backBoard/FSMC.scala @@ -4,22 +4,8 @@ import chisel3._ import chisel3.util._ -class FSMC_Port_Bundle extends Bundle{ - // val clk = Input(Bool()) - val addr = Input(UInt(2.W)) - val dataIn = Input(UInt(8.W)) - val dataOut = Output(UInt(8.W)) - val dataOEn = Output(Bool()) - val cen = Input(Bool()) - val oen = Input(Bool()) - val wen = Input(Bool()) -} -// class FSMC_Status_Bundle extends Bundle{ -// val op = UInt(2.W) -// val isBusy = Bool() -// val isError = Bool() -// } + class FSMCSlvIO extends Bundle{ @@ -29,55 +15,28 @@ class FSMCSlvIO extends Bundle{ val CDROut = Valid(new CDRData) } -class FSMCSlv extends Module{ +class FSMCSlvBase extends Module{ val io: FSMCSlvIO = IO(new FSMCSlvIO) - val fsmcAddrSync = ShiftRegister( io.FSMC.addr, 2, 0.U, true.B ) - val fsmcdataInSync = ShiftRegister( io.FSMC.dataIn, 2, 0.U, true.B ) - val fsmcCEnSync = ShiftRegister( io.FSMC.cen, 2, true.B, true.B ) - val fsmcOEnSync = ShiftRegister( io.FSMC.oen, 2, true.B, true.B ) - val fsmcWEnSync = ShiftRegister( io.FSMC.wen, 2, true.B, true.B ) - - io.FSMC.dataOEn := io.FSMC.oen - val status = RegInit(0.U(8.W)) - val address = Reg(UInt(8.W)) - val data = Reg(UInt(8.W)) - val none = Reg(UInt(8.W)) - - val dataOutReg = RegInit(0.U(8.W)); io.FSMC.dataOut := dataOutReg - when( ~fsmcCEnSync & ~fsmcOEnSync ){ - dataOutReg := - Mux1H(Seq( - (fsmcAddrSync === 0.U) -> status, - (fsmcAddrSync === 1.U) -> address, - (fsmcAddrSync === 2.U) -> data, - (fsmcAddrSync === 3.U) -> none, - )) - } .elsewhen( ~fsmcCEnSync & ~fsmcWEnSync ){ - when( fsmcAddrSync === 0.U ){ - status := fsmcdataInSync - } - when( fsmcAddrSync === 1.U ){ - address := fsmcdataInSync - } - when( fsmcAddrSync === 2.U ){ - data := fsmcdataInSync - } - when( fsmcAddrSync === 3.U ){ - none := fsmcdataInSync - } - } - when( io.CDRIn.fire ){ - - } - + + + mirror.io.datar_b, + mirror.io.ce_b, + mirror.io.we_b, + mirror.io.[10:0] addr_b, + mirror.io.[7:0] dataw_b +} + +trait MirrorSRAM { this: FSMCSlvBase => + } + diff --git a/src/main/scala/backBoard/MirrorSRAM.scala b/src/main/scala/backBoard/MirrorSRAM.scala new file mode 100644 index 0000000..6f1bed9 --- /dev/null +++ b/src/main/scala/backBoard/MirrorSRAM.scala @@ -0,0 +1,100 @@ +package BACK + +import chisel3._ +import chisel3.util._ + + + + +class MirrorSRAMIO extends Bundle{ + + val datar_a = Output(UInt(8.W)) + val datar_b = Output(UInt(8.W)) + + val clk_a = Input(Bool()) + val clk_b = Input(Bool()) + + val reset_a = Input(Bool()) + val reset_b = Input(Bool()) + + val ce_a = Input(Bool()) + val ce_b = Input(Bool()) + + val we_a = Input(Bool()) + val we_b = Input(Bool()) + + val addr_a = Input(UInt(11.W)) + val addr_b = Input(UInt(11.W)) + + val dataw_a = Input(UInt(8.W)) + val dataw_b = Input(UInt(8.W)) +} + +class MirrorSRAM extends BlackBox with HasBlackBoxInline { + + val io: MirrorSRAM = IO(new MirrorSRAM) + + setInline("lvds_bus_master.v", + """ + | module MirrorSRAM( + | output [7:0] datar_a, + | output [7:0] datar_b, + | + | input clock, + | input reset, + | + | input ce_a, + | input ce_b, + | + | input we_a, + | input we_b, + | + | input [10:0] addr_a, + | input [10:0] addr_b, + | + | input [7:0] dataw_a + | input [7:0] dataw_b + | ); + | + | wire [15:0] doa; + | wire [15:0] dob; + | + + | + | assign datar_a = doa[7:0]; + | assign datar_b = dob[7:0]; + | + | DPB bram_dpb_0 ( + | .DOA(doa), + | .DOB(dob), + | .CLKA(clock), + | .OCEA(1'b1), + | .CEA(ce_a), + | .RESETA(reset), + | .WREA(we_a), + | .CLKB(clock), + | .OCEB(1'b1), + | .CEB(ce_b), + | .RESETB(reset), + | .WREB( we_b ), + | .BLKSELA(3'b0), + | .BLKSELB(3'b0), + | .ADA({addr_a[10:0],3'b000}), + | .DIA({8'b0,dataw_a}), + | .ADB({addr_b[10:0],3'b000}), + | .DIB({8'b0,dataw_b}) + | ); + | + | defparam bram_dpb_0.READ_MODE0 = 1'b0; + | defparam bram_dpb_0.READ_MODE1 = 1'b0; + | defparam bram_dpb_0.WRITE_MODE0 = 2'b00; + | defparam bram_dpb_0.WRITE_MODE1 = 2'b00; + | defparam bram_dpb_0.BIT_WIDTH_0 = 8; + | defparam bram_dpb_0.BIT_WIDTH_1 = 8; + | defparam bram_dpb_0.RESET_MODE = "SYNC"; + | + | ); + |endmodule + """.stripMargin) +} +