改异步复位，增加flush接口，删除其他工程代码以编译通过

src/main/scala/backBoard/shin/SpiInterface.scala

@@ -28,7 +28,7 @@ class RegAccessInterfaceIO extends Bundle{
   val isEnR   = Output(Bool())
 }
 
-abstract class SpiInterfaceBase extends Module{
+abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
   val io = IO(new RegAccessInterfaceIO)
 
   val sck     = Wire(Bool())