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改异步复位，增加flush接口，删除其他工程代码以编译通过

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This commit is contained in:
Ruige Lee
2025-08-25 19:16:27 +08:00
parent bca9724c3c
commit 6f1101f6dc
36 changed files with 615 additions and 4418 deletions
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12
src/main/scala/backBoard/shin/ShinTop.scala
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@@ -49,7 +49,7 @@ class ShinTopIO extends Bundle{
abstract class ShinTopBase extends Module{
abstract class ShinTopBase extends Module with RequireAsyncReset{
val io: ShinTopIO = IO(new ShinTopIO)
@@ -160,7 +160,7 @@ abstract class ShinTopBase extends Module{
for( i <- 0 until 8 ){
interface.io.smUsedDepth(i) := smUnit(i).io.cnt
smUnit(i).reset := reset.asBool | interface.io.isSMReset(i)
smUnit(i).io.flush := interface.io.isSMReset(i)
}
@@ -380,10 +380,10 @@ trait ShinTopSlave{ this: ShinTopBase =>
slaveParser.io.intHWClr(0) := interface.io.intHWTrig(0) & interface.io.intHWClr(0)
slaveParser.io.intHWClr(1) := interface.io.intHWTrig(1) & interface.io.intHWClr(1)
downCDRIn.reset := reset.asBool | RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) )
upCDRIn.reset := reset.asBool | RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) )
downCDROut.reset := reset.asBool | RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) )
upCDROut.reset := reset.asBool | RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) )
downCDRIn.io.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) )
upCDRIn.io.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) )
downCDROut.io.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) )
upCDROut.io.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) )
interface.io.lvds <> slaveParser.io.lvds