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改异步复位，增加flush接口，删除其他工程代码以编译通过

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This commit is contained in:
Ruige Lee
2025-08-25 19:16:27 +08:00
parent bca9724c3c
commit 6f1101f6dc
36 changed files with 615 additions and 4418 deletions
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2
src/main/scala/backBoard/shin/Interface.scala
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@@ -213,7 +213,7 @@ class InterfaceIO extends Bundle{
}
abstract class InterfaceBase extends Module{
abstract class InterfaceBase extends Module with RequireAsyncReset{
val io: InterfaceIO = IO(new InterfaceIO)
val oSpi = Module(new SSpiInterface)

6
src/main/scala/backBoard/shin/MasterParser.scala
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@@ -27,7 +27,7 @@ class MasterParserIO extends Bundle{
}
abstract class MasterParserBase extends Module{
abstract class MasterParserBase extends Module with RequireAsyncReset{
val io: MasterParserIO = IO(new MasterParserIO)
val txCnt = Reg(UInt(12.W))
@@ -167,11 +167,11 @@ abstract class MasterParserBase extends Module{
txcrc.io.isEnable := io.downOut.fire & txCnt < txLen
txcrc.io.dataIn := io.downOut.bits.tdata
txcrc.reset := reset.asBool | reqReady
txcrc.io.flush := reqReady
rxcrc.io.isEnable := io.upIn.fire & rxCnt < rxLen
rxcrc.io.dataIn := io.upIn.bits.tdata
rxcrc.reset := reset.asBool | io.rsp.fire
rxcrc.io.flush := io.rsp.fire

19
src/main/scala/backBoard/shin/SMUnit.scala
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@@ -33,9 +33,11 @@ class SMUnitIO(depth: Int) extends Bundle {
val sram = Flipped(Vec(depth, new SRAM2kIO))
val cnt = Output(UInt(8.W))
val flush = Input(Bool())
}
abstract class SMUnitBase(depth: Int = 4) extends Module {
abstract class SMUnitBase(depth: Int = 4) extends Module with RequireAsyncReset{
val io: SMUnitIO = IO(new SMUnitIO(depth))
@@ -43,18 +45,19 @@ abstract class SMUnitBase(depth: Int = 4) extends Module {
val rPtr = RegInit(0.U((log2Ceil(depth)+1).W))
val isFull = (wPtr ^ rPtr) === (1.U << log2Ceil(depth))
// ( wPtr.extract(2) =/= rPtr.extract(2) ) & ( wPtr(1,0) === rPtr(1,0) )
val isEmpty = ( wPtr === rPtr )
when( io.enq & ~isFull ){
when(io.flush){
wPtr := 0.U
} .elsewhen( io.enq & ~isFull ){
wPtr := wPtr + 1.U
// assert( ~isFull)
}
when( io.deq & ~isEmpty ){
when(io.flush){
rPtr := 0.U
} .elsewhen( io.deq & ~isEmpty ){
rPtr := rPtr + 1.U
// assert( ~isEmpty )
}
@@ -87,7 +90,9 @@ abstract class SMUnitBase(depth: Int = 4) extends Module {
val cnt = RegInit(0.U((log2Ceil(depth+1)).W)); io.cnt := cnt
when( io.enq & ~isFull ){
when( io.flush ){
cnt := 0.U
} .elsewhen( io.enq & ~isFull ){
cnt := cnt + 1.U
assert(cnt =/= depth.U)
} .elsewhen( io.deq & ~isEmpty ){

12
src/main/scala/backBoard/shin/ShinTop.scala
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@@ -49,7 +49,7 @@ class ShinTopIO extends Bundle{
abstract class ShinTopBase extends Module{
abstract class ShinTopBase extends Module with RequireAsyncReset{
val io: ShinTopIO = IO(new ShinTopIO)
@@ -160,7 +160,7 @@ abstract class ShinTopBase extends Module{
for( i <- 0 until 8 ){
interface.io.smUsedDepth(i) := smUnit(i).io.cnt
smUnit(i).reset := reset.asBool | interface.io.isSMReset(i)
smUnit(i).io.flush := interface.io.isSMReset(i)
}
@@ -380,10 +380,10 @@ trait ShinTopSlave{ this: ShinTopBase =>
slaveParser.io.intHWClr(0) := interface.io.intHWTrig(0) & interface.io.intHWClr(0)
slaveParser.io.intHWClr(1) := interface.io.intHWTrig(1) & interface.io.intHWClr(1)
downCDRIn.reset := reset.asBool | RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) )
upCDRIn.reset := reset.asBool | RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) )
downCDROut.reset := reset.asBool | RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) )
upCDROut.reset := reset.asBool | RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) )
downCDRIn.io.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) )
upCDRIn.io.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) )
downCDROut.io.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) )
upCDROut.io.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) )
interface.io.lvds <> slaveParser.io.lvds

10
src/main/scala/backBoard/shin/SlaveParser.scala
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@@ -82,7 +82,7 @@ class SlaveParserIO extends Bundle{
val upRecStat = Output(new Stat_IO_Bundle)
}
abstract class SlaveParserBase extends Module{
abstract class SlaveParserBase extends Module with RequireAsyncReset{
val io: SlaveParserIO = IO(new SlaveParserIO)
val sReg = io.sReg
@@ -991,11 +991,11 @@ with SlaveParserProbe{
io.intHWTrig(0) := downRecParser.io.isError
io.intHWTrig(1) := upRecParser.io.isError
downRecParser.reset := reset.asBool | RegNext(downRecParser.io.isError & io.intHWClr(0))
downSendGen.reset := reset.asBool | RegNext(downRecParser.io.isError & io.intHWClr(0))
downRecParser.io.flush := RegNext(downRecParser.io.isError & io.intHWClr(0))
downSendGen.io.flush := RegNext(downRecParser.io.isError & io.intHWClr(0))
upRecParser.reset := reset.asBool | RegNext(upRecParser.io.isError & io.intHWClr(1))
upSendGen.reset := reset.asBool | RegNext(upRecParser.io.isError & io.intHWClr(1))
upRecParser.io.flush := RegNext(upRecParser.io.isError & io.intHWClr(1))
upSendGen.io.flush := RegNext(upRecParser.io.isError & io.intHWClr(1))
io.downRecStat := downRecParser.io.stat
io.upRecStat := upRecParser.io.stat

68
src/main/scala/backBoard/shin/SlaveRecParser.scala
View File

@@ -20,10 +20,10 @@ class SlaveRecParserIO extends Bundle{
val stat = Output(new Stat_IO_Bundle)
val flush = Input(Bool())
}
class SlaveRecParser extends Module{
class SlaveRecParser extends Module with RequireAsyncReset{
val io: SlaveRecParserIO = IO(new SlaveRecParserIO)
val crc = Module(new crc32_8)
@@ -53,7 +53,7 @@ class SlaveRecParser extends Module{
crc.io.dataIn := io.rec.bits.tdata
crc.reset := reset.asBool | stateCurr === STATE_IDLE
crc.io.flush := stateCurr === STATE_IDLE | io.flush
val crcData = Reg(UInt(32.W))
val isCrcPass = crc.io.crc === Cat( crcData(23,0), io.rec.bits.tdata )
@@ -96,7 +96,9 @@ class SlaveRecParser extends Module{
io.subMsgTailReq.bits.workCnt := subMsgTail.workCnt | io.rec.bits.tdata(7,0)
when( io.rec.fire ){
when( io.flush ){
lengthCnt := 0.U
} .elsewhen( io.rec.fire ){
when( stateCurr =/= stateNext ){
lengthCnt := 0.U
} .otherwise{
@@ -177,36 +179,38 @@ class SlaveRecParser extends Module{
stateNext :=
Mux1H(Seq(
//必须使用上升沿触发，以避免前一帧长度超过预期
( stateCurr === STATE_IDLE ) -> Mux( ~RegNext(io.rec.valid) & io.rec.valid, STATE_HEADER, STATE_IDLE ),
( stateCurr === STATE_HEADER ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR,
Mux( lengthCnt === (4-1).U,
MuxCase( STATE_ERROR, Array(
( frameHeader.frameStyle === FRAME_STYLE_COMMON ) -> STATE_SUBMSG_HEADER,
( frameHeader.frameStyle === FRAME_STYLE_PROBE ) -> STATE_CRC,
Mux( io.flush, STATE_IDLE,
Mux1H(Seq(
//必须使用上升沿触发，以避免前一帧长度超过预期
( stateCurr === STATE_IDLE ) -> Mux( ~RegNext(io.rec.valid) & io.rec.valid, STATE_HEADER, STATE_IDLE ),
( stateCurr === STATE_HEADER ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR,
Mux( lengthCnt === (4-1).U,
MuxCase( STATE_ERROR, Array(
( frameHeader.frameStyle === FRAME_STYLE_COMMON ) -> STATE_SUBMSG_HEADER,
( frameHeader.frameStyle === FRAME_STYLE_PROBE ) -> STATE_CRC,
)), STATE_HEADER
)), STATE_HEADER
)), STATE_HEADER
),
( stateCurr === STATE_SUBMSG_HEADER ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR,
Mux( lengthCnt === (6-1).U, STATE_PAYLOAD_DATA, STATE_SUBMSG_HEADER )
), STATE_SUBMSG_HEADER),
( stateCurr === STATE_PAYLOAD_DATA ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast | isDataRejErr, STATE_ERROR,
Mux( lengthCnt === ( subMsgHeader.length - 1.U), STATE_SUBMSG_TAIL, STATE_PAYLOAD_DATA )
), STATE_PAYLOAD_DATA),
( stateCurr === STATE_SUBMSG_TAIL ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR,
Mux( lengthCnt === ( (2 - 1).U),
Mux( frameLenCnt === frameHeader.frameLenAim - 1.U, STATE_CRC, STATE_SUBMSG_HEADER
),STATE_SUBMSG_TAIL )
), STATE_SUBMSG_TAIL),
( stateCurr === STATE_CRC ) -> Mux( io.rec.fire & io.rec.bits.tlast,
Mux( lengthCnt === (4 - 1).U & isCrcPass, STATE_IDLE, STATE_ERROR ), STATE_CRC
),
( stateCurr === STATE_SUBMSG_HEADER ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR,
Mux( lengthCnt === (6-1).U, STATE_PAYLOAD_DATA, STATE_SUBMSG_HEADER )
), STATE_SUBMSG_HEADER),
( stateCurr === STATE_PAYLOAD_DATA ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast | isDataRejErr, STATE_ERROR,
Mux( lengthCnt === ( subMsgHeader.length - 1.U), STATE_SUBMSG_TAIL, STATE_PAYLOAD_DATA )
), STATE_PAYLOAD_DATA),
( stateCurr === STATE_SUBMSG_TAIL ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR,
Mux( lengthCnt === ( (2 - 1).U),
Mux( frameLenCnt === frameHeader.frameLenAim - 1.U, STATE_CRC, STATE_SUBMSG_HEADER
),STATE_SUBMSG_TAIL )
), STATE_SUBMSG_TAIL),
( stateCurr === STATE_CRC ) -> Mux( io.rec.fire & io.rec.bits.tlast,
Mux( lengthCnt === (4 - 1).U & isCrcPass, STATE_IDLE, STATE_ERROR ), STATE_CRC
),
( stateCurr === STATE_ERROR ) -> STATE_ERROR,
))
( stateCurr === STATE_ERROR ) -> STATE_ERROR,
))
)

55
src/main/scala/backBoard/shin/SlaveSendGen.scala
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@@ -22,12 +22,14 @@ class SlaveSendGenIO extends Bundle{
val isError = Output(Bool())
val stateCurr = Output(UInt(3.W))
val flush = Input(Bool())
}
class SlaveSendGen extends Module{
class SlaveSendGen extends Module with RequireAsyncReset{
val io: SlaveSendGenIO = IO(new SlaveSendGenIO)
@@ -60,7 +62,7 @@ class SlaveSendGen extends Module{
crc.reset := reset.asBool | stateCurr === STATE_IDLE
crc.io.flush := stateCurr === STATE_IDLE | io.flush
@@ -112,30 +114,33 @@ class SlaveSendGen extends Module{
assert( ~(io.subMsgTailReq.ready & ~io.subMsgTailReq.valid) )
stateNext := Mux1H(Seq(
(stateCurr === STATE_IDLE) -> Mux( io.frameReq.fire, STATE_FRAME_HEADER, STATE_IDLE ),
(stateCurr === STATE_FRAME_HEADER) -> Mux( io.send.fire, Mux( lengthCnt === (4-1).U, Mux(
frameInfo.frameStyle === FRAME_STYLE_COMMON,
Mux(io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT),
STATE_CRC ),
STATE_FRAME_HEADER), STATE_FRAME_HEADER ),
(stateCurr === STATE_SUBMSG_HEADER) -> Mux( io.send.fire, Mux( lengthCnt === (6-1).U, STATE_SUBMSG_DATA, STATE_SUBMSG_HEADER), STATE_SUBMSG_HEADER),
(stateCurr === STATE_SUBMSG_DATA) -> Mux( io.send.fire,
Mux( lengthCnt === subMsgHeadInfo.length-1.U, STATE_SUBMSG_TAIL, STATE_SUBMSG_DATA ), //已经发送完成该子报文
STATE_SUBMSG_DATA ),
(stateCurr === STATE_SUBMSG_TAIL) -> Mux( io.send.fire,
Mux( lengthCnt === (2-1).U, //已经发送完成该子报文尾
Mux( frameLenCnt === frameInfo.frameLenAim -1.U, STATE_CRC, //主报文长度达到， 进CRC
Mux( io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT ) ), //主报文长度未到，进下一个子报文
STATE_SUBMSG_TAIL
), STATE_SUBMSG_TAIL ),
stateNext :=
Mux( io.flush, STATE_IDLE,
Mux1H(Seq(
(stateCurr === STATE_IDLE) -> Mux( io.frameReq.fire, STATE_FRAME_HEADER, STATE_IDLE ),
(stateCurr === STATE_FRAME_HEADER) -> Mux( io.send.fire, Mux( lengthCnt === (4-1).U, Mux(
frameInfo.frameStyle === FRAME_STYLE_COMMON,
Mux(io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT),
STATE_CRC ),
STATE_FRAME_HEADER), STATE_FRAME_HEADER ),
(stateCurr === STATE_SUBMSG_HEADER) -> Mux( io.send.fire, Mux( lengthCnt === (6-1).U, STATE_SUBMSG_DATA, STATE_SUBMSG_HEADER), STATE_SUBMSG_HEADER),
(stateCurr === STATE_SUBMSG_DATA) -> Mux( io.send.fire,
Mux( lengthCnt === subMsgHeadInfo.length-1.U, STATE_SUBMSG_TAIL, STATE_SUBMSG_DATA ), //已经发送完成该子报文
STATE_SUBMSG_DATA ),
(stateCurr === STATE_SUBMSG_TAIL) -> Mux( io.send.fire,
Mux( lengthCnt === (2-1).U, //已经发送完成该子报文尾
Mux( frameLenCnt === frameInfo.frameLenAim -1.U, STATE_CRC, //主报文长度达到， 进CRC
Mux( io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT ) ), //主报文长度未到，进下一个子报文
STATE_SUBMSG_TAIL
), STATE_SUBMSG_TAIL ),
(stateCurr === STATE_CRC) -> Mux( io.send.fire, Mux( lengthCnt === (4-1).U, STATE_IDLE, STATE_CRC ), STATE_CRC),
// (stateCurr === STATE_ERROR) -> Mux( io.send.fire, STATE_IDLE, STATE_ERROR),
(stateCurr === STATE_WAIT) -> Mux( io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT),
))
(stateCurr === STATE_CRC) -> Mux( io.send.fire, Mux( lengthCnt === (4-1).U, STATE_IDLE, STATE_CRC ), STATE_CRC),
// (stateCurr === STATE_ERROR) -> Mux( io.send.fire, STATE_IDLE, STATE_ERROR),
(stateCurr === STATE_WAIT) -> Mux( io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT),
))
)
io.data(0).ready := io.send.fire & (stateCurr === STATE_SUBMSG_DATA) & (subMsgHeadInfo.source === 0.U)
io.data(1).ready := io.send.fire & (stateCurr === STATE_SUBMSG_DATA) & (subMsgHeadInfo.source === 1.U)

2
src/main/scala/backBoard/shin/SpiInterface.scala
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@@ -28,7 +28,7 @@ class RegAccessInterfaceIO extends Bundle{
val isEnR = Output(Bool())
}
abstract class SpiInterfaceBase extends Module{
abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
val io = IO(new RegAccessInterfaceIO)
val sck = Wire(Bool())