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改异步复位，增加flush接口，删除其他工程代码以编译通过

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This commit is contained in:
Ruige Lee
2025-08-25 19:16:27 +08:00
parent bca9724c3c
commit 6f1101f6dc
36 changed files with 615 additions and 4418 deletions
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23
src/main/scala/backBoard/ebus/CDROut.scala
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@@ -14,11 +14,13 @@ class CDROutIO extends Bundle{
val axis = Flipped(Decoupled(new AXIS_Bundle(8)))
val serDat = Output(Bool())
val flush = Input(Bool())
}
class CDROut extends Module{
class CDROut extends Module with RequireAsyncReset{
val io: CDROutIO = IO(new CDROutIO)
def PRE_NUM = 3 //PRE_NUM should >= 3
@@ -39,12 +41,14 @@ class CDROut extends Module{
val shiftData = RegInit(0.U(10.W))
stateNext := Mux1H(Seq(
(stateCurr === STATE_IDLE) -> ( Mux( io.axis.valid, STATE_PREAMBLE, STATE_IDLE )),
(stateCurr === STATE_PREAMBLE) -> ( Mux( (byteCnt === (PRE_NUM-1).U) & (bitCnt === 9.U), Mux( io.axis.valid, STATE_PAYLOAD, STATE_IDLE), STATE_PREAMBLE )),
(stateCurr === STATE_PAYLOAD) -> ( Mux( (io.axis.fire & io.axis.bits.tlast) | (~io.axis.valid & io.axis.ready), STATE_IDLE, STATE_PAYLOAD ) ),
))
stateNext :=
Mux( io.flush, STATE_IDLE,
Mux1H(Seq(
(stateCurr === STATE_IDLE) -> ( Mux( io.axis.valid, STATE_PREAMBLE, STATE_IDLE )),
(stateCurr === STATE_PREAMBLE) -> ( Mux( (byteCnt === (PRE_NUM-1).U) & (bitCnt === 9.U), Mux( io.axis.valid, STATE_PAYLOAD, STATE_IDLE), STATE_PREAMBLE )),
(stateCurr === STATE_PAYLOAD) -> ( Mux( (io.axis.fire & io.axis.bits.tlast) | (~io.axis.valid & io.axis.ready), STATE_IDLE, STATE_PAYLOAD ) ),
))
)
io.serDat := shiftData.extract(9)
io.axis.ready :=
bitCnt === 9.U & (
@@ -58,8 +62,9 @@ class CDROut extends Module{
}
when( stateCurr === STATE_IDLE & stateNext === STATE_PREAMBLE){ //PRE
when( io.flush ){
shiftData := 0.U
} .elsewhen( stateCurr === STATE_IDLE & stateNext === STATE_PREAMBLE){ //PRE
shiftData := ETH_PRE
} .otherwise{
when( bitCnt =/= 9.U ){