改异步复位，增加flush接口，删除其他工程代码以编译通过

src/main/scala/backBoard/ebus/CDRIn.scala

@@ -8,11 +8,11 @@ import chisel3.util._
 class CDRInIO extends Bundle{
   val axis = Decoupled(new AXIS_Bundle(8))
   val serDat = Input(Bool())
-
+  val flush = Input(Bool())
 }
 
 
-abstract class CDRInBase extends Module{
+abstract class CDRInBase extends Module with RequireAsyncReset{
 
 
   val io: CDRInIO = IO(new CDRInIO)
@@ -21,48 +21,6 @@ abstract class CDRInBase extends Module{
   val syncSerDat = Wire(Bool())
 }
 
-trait CDRInOverSample{ this: CDRInBase =>
-
-  val overCLK = IO(Input(Bool()))
-  val sampleRate: Int = 4
-  require(sampleRate >= 4)
-
-  val sampleReg = withClockAndReset(overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate+3 ) }
-
-  val flitReg = for( i <- 0 until sampleRate ) yield {
-    withClockAndReset(overCLK.asClock, reset.asBool){
-      RegNext(
-        (sampleReg(i) & sampleReg(i+1)) |
-        (sampleReg(i) & sampleReg(i+2)) |
-        (sampleReg(i+1) & sampleReg(i+2)), false.B
-      )
-    }
-  }
-
-  val arbCnt  = withClockAndReset(overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) }
-  arbCnt := Cat( arbCnt(sampleRate-2,0), arbCnt.extract(sampleRate-1) )
-  val arbLock = withClockAndReset(overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) }
-  withClockAndReset(overCLK.asClock, reset.asBool){
-    when( flitReg(0) ^ flitReg(1) ){
-      arbLock := arbCnt
-    }
-
-
-  }
-
-  val asyncSerDat = withClockAndReset(overCLK.asClock, reset.asBool){ RegNext(
-    Mux1H(
-      (for { i <- 0 until sampleRate; j <- 0 until sampleRate } yield {
-        //跳变沿到来锁定的位置        锁定拍当前所在的位置          选择锁定拍后一拍的值认为是正确值
-        ((arbLock === (1.U << i)) & (arbCnt === (1.U << j))) -> flitReg((sampleRate + 2 - i + j) % sampleRate)
-      })
-    )
-  )}
-
-
-  syncSerDat := ShiftRegister( asyncSerDat, 2 )
-
-}
 
 trait CDRInMultiSample{ this: CDRInBase =>
   
@@ -133,8 +91,6 @@ trait CDRInMultiSample{ this: CDRInBase =>
 
   //优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的
 
-      // val diff = Wire(UInt( (log2Ceil(clkNum)).W ))
-      // diff := arbLock - j.U
       when( ~isLock ){
         for( i <- 3 until 19 ){
           val j = 19 - i - 1
@@ -156,7 +112,9 @@ trait CDRInMultiSample{ this: CDRInBase =>
         }
       }
 
-  when( ~isLock ){
+  when( io.flush ){
+    isLock := false.B
+  } .elsewhen( ~isLock ){
     for( i <- 3 until 19 ){
       val j = 19 - i - 1
       when( flitReg(j) ^ flitReg(j+1) ){
@@ -199,23 +157,34 @@ trait CDRInAxis{ this: CDRInBase =>
   val bitCnt = Reg(UInt(4.W))
   val byteCnt = RegInit(0.U((12+1).W))
 
-  val checkSFD = RegInit( 0.U(20.W) ); checkSFD := Cat( checkSFD(18,0), syncSerDat )
+  val checkSFD = RegInit( 0.U(20.W) )
+
+  when( io.flush ){
+    checkSFD := 0.U
+  } .otherwise{
+    checkSFD := Cat( checkSFD(18,0), syncSerDat )
+  }
 
   val shiftData = Dualb4b5Decoder(checkSFD(9,0))
 
   val payloadLen = RegInit(0.U(12.W))
-  when( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
+
+  when( io.flush ){
+    payloadLen := 0.U
+  } .elsewhen( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
     payloadLen := Cat( shiftData, 0.U(4.W) )
   } .elsewhen( byteCnt === 1.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
     payloadLen := Cat( payloadLen(11,4), shiftData(7,4) )
   }
   
   stateNext := 
-    Mux1H(Seq(
-      (stateCurr === STATE_IDLE)    -> ( Mux( checkSFD === Cat(ETH_PRE , ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE
-      (stateCurr === STATE_HEADER)  -> ( Mux( (byteCnt === (HeaderByte-1).U)   & (bitCnt === 9.U), STATE_PAYLOAD, STATE_HEADER ) ),
-      (stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen + (4 - 1).U)  ) & (bitCnt === 9.U), STATE_IDLE, STATE_PAYLOAD  )), // PAYLOAD
-    ))                                                                  //crc
+    Mux( io.flush, STATE_IDLE,
+      Mux1H(Seq(
+        (stateCurr === STATE_IDLE)    -> ( Mux( checkSFD === Cat(ETH_PRE , ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE
+        (stateCurr === STATE_HEADER)  -> ( Mux( (byteCnt === (HeaderByte-1).U)   & (bitCnt === 9.U), STATE_PAYLOAD, STATE_HEADER ) ),
+        (stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen + (4 - 1).U)  ) & (bitCnt === 9.U), STATE_IDLE, STATE_PAYLOAD  )), // PAYLOAD
+      ))                                                                  //crc
+    )
 
 
 
@@ -231,7 +200,9 @@ trait CDRInAxis{ this: CDRInBase =>
     }
   }
 
-  when( stateCurr === STATE_IDLE & ( checkSFD === Cat(ETH_PRE, ETH_SFD) ) ){ //first align
+  when( io.flush ){
+    byteCnt := 0.U
+  } .elsewhen( stateCurr === STATE_IDLE & ( checkSFD === Cat(ETH_PRE, ETH_SFD) ) ){ //first align
     byteCnt := 0.U
   } .elsewhen( bitCnt === 9.U ){
     when( stateCurr === STATE_HEADER ){
@@ -250,26 +221,29 @@ trait CDRInAxis{ this: CDRInBase =>
   val axis_valid = RegInit(false.B)
   val axis_tdata = RegEnable( shiftData, bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) )
   val axis_tuser = false.B
-  val axis_tlast = RegNext( stateCurr === STATE_PAYLOAD & stateNext === STATE_IDLE, false.B )
+  val axis_tlast = RegInit( false.B )
+
+
 
   io.axis.valid := axis_valid
   io.axis.bits.tdata := axis_tdata
   io.axis.bits.tuser := axis_tuser
   io.axis.bits.tlast := axis_tlast
 
-
-  when( io.axis.fire ){
+  when( io.flush ){
+    axis_valid := false.B
+  } .elsewhen( io.axis.fire ){
     axis_valid := false.B
   } .elsewhen( bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) ){
     axis_valid := true.B
   }
 
-}
+  when( io.flush ){
+    axis_tlast := false.B
+  } .otherwise{
+    axis_tlast := (stateCurr === STATE_PAYLOAD & stateNext === STATE_IDLE)
+  }
 
-class CDRIn extends CDRInBase 
-with CDRInAxis
-with CDRInOverSample{
-  require(false)
 }
 
 class MPCDRIn extends CDRInBase