From 6efd11322bdc5c46a5611dddc2ee507a38e3a137 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Tue, 4 Jul 2023 14:26:24 +0800 Subject: [PATCH] io merge --- src/main/scala/mac/MAC.scala | 35 +------------ src/main/scala/mac/MII.scala | 7 +-- src/main/scala/mac/MacBundle.scala | 78 ++++++++++++++++++++++++++++ src/main/scala/mac/MacTilelink.scala | 51 ++---------------- 4 files changed, 84 insertions(+), 87 deletions(-) create mode 100644 src/main/scala/mac/MacBundle.scala diff --git a/src/main/scala/mac/MAC.scala b/src/main/scala/mac/MAC.scala index f616490..b8f47af 100644 --- a/src/main/scala/mac/MAC.scala +++ b/src/main/scala/mac/MAC.scala @@ -28,34 +28,7 @@ class Mac(implicit p: Parameters) extends LazyModule with HasMacParameters{ } -trait MacWishboneMasterIO{ this: Bundle => - val m_wb_adr_o = Output(UInt(32.W)) - val m_wb_sel_o = Output(UInt(4.W)) - val m_wb_we_o = Output(Bool()) - val m_wb_dat_i = Input(UInt(32.W)) - val m_wb_dat_o = Output(UInt(32.W)) - val m_wb_cyc_o = Output(Bool()) - val m_wb_stb_o = Output(Bool()) - val m_wb_ack_i = Input(Bool()) - val m_wb_err_i = Input(Bool()) - val m_wb_cti_o = Output(UInt(3.W)) - val m_wb_bte_o = Output(UInt(2.W)) -} -trait MacWishboneSlaveIO{ this: Bundle => - val WB_DAT_I = Input(UInt(32.W)) // WISHBONE data input - val WB_DAT_O = Output(UInt(32.W)) // WISHBONE data output - - val WB_ADR_I = Input(UInt(12.W)) // WISHBONE address input - val WB_WE_I = Input(Bool()) // WISHBONE write enable input - - val WB_SEL_I = Input(UInt(4.W)) // WISHBONE byte select input - val WB_CYC_I = Input(Bool()) // WISHBONE cycle input - val WB_STB_I = Input(Bool()) // WISHBONE strobe input - - val WB_ACK_O = Output(Bool()) // WISHBONE acknowledge output - val WB_ERR_O = Output(Bool()) // WISHBONE error output -} class MacIO extends Bundle{ // Tx @@ -74,8 +47,6 @@ class MacIO extends Bundle{ val mcoll_pad_i = Input(Bool()) val mcrs_pad_i = Input(Bool()) - - val int_o = Output(Bool()) } @@ -85,7 +56,6 @@ class MacImp(outer: Mac) extends LazyModuleImp(outer){ //( if(!isTileLink) { IO(new MacIO with MDIO with MacWishboneMasterIO with MacWishboneSlaveIO) } //else {IO(new MacIO with MDIO with MacWishboneMasterIO)} ) -val m_wb_adr_tmp = Wire(UInt(30.W)) val r_ClkDiv = Wire(UInt(8.W)) val r_MiiNoPre = Wire(Bool()) val r_CtrlData = Wire(UInt(16.W)) @@ -103,7 +73,6 @@ val RStatStart = Wire(Bool()) val UpdateMIIRX_DATAReg = Wire(Bool()) -dontTouch( m_wb_adr_tmp ) dontTouch( r_ClkDiv ) dontTouch( r_MiiNoPre ) dontTouch( r_CtrlData ) @@ -705,7 +674,7 @@ val rxethmac = Module(new MacRx) io.WB_ERR_O := wishbone.io.WB_ERR_O - m_wb_adr_tmp := wishbone.io.m_wb_adr_o + io.m_wb_adr_o := wishbone.io.m_wb_adr_o io.m_wb_sel_o := wishbone.io.m_wb_sel_o io.m_wb_we_o := wishbone.io.m_wb_we_o io.m_wb_dat_o := wishbone.io.m_wb_dat_o @@ -771,8 +740,6 @@ val rxethmac = Module(new MacRx) - io.m_wb_adr_o := Cat(m_wb_adr_tmp, 0.U(2.W)) - val macstatus = Module(new MacStatus) macstatus.io.reset := reset.asBool diff --git a/src/main/scala/mac/MII.scala b/src/main/scala/mac/MII.scala index d98ee15..96f2f71 100644 --- a/src/main/scala/mac/MII.scala +++ b/src/main/scala/mac/MII.scala @@ -3,12 +3,7 @@ package MAC import chisel3._ import chisel3.util._ -trait MDIO { this: Bundle => - val mdi = Input( Bool()) // MII Management Data In - val mdc = Output(Bool()) // MII Management Data Clock - val mdo = Output(Bool()) // MII Management Data Output - val mdoEn = Output(Bool()) // MII Management Data Output Enable -} + class MIIMIO extends Bundle with MDIO{ val Divider = Input( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0]) diff --git a/src/main/scala/mac/MacBundle.scala b/src/main/scala/mac/MacBundle.scala new file mode 100644 index 0000000..6affd8b --- /dev/null +++ b/src/main/scala/mac/MacBundle.scala @@ -0,0 +1,78 @@ +package MAC + +import chisel3._ +import chisel3.util._ + + + + +class TxBuffDesc extends Bundle{ + val len = UInt(16.W) //[31.16] + val rd = Bool() //[15] + val irq = Bool() //14 + val wr = Bool() //13 + val pad = Bool() //12 + val crc = Bool() //11 + val reserved1 = UInt(2.W) //10,9 + val ur = Bool() //8 + val rtry = UInt(4.W) //7 6 5 4 + val rl = Bool() //3 + val lc = Bool() //2 + val df = Bool() //1 + val cs = Bool() //0 +} + +class RxBuffDesc extends Bundle{ + val len = UInt(16.W) //[31.16] + val e = Bool() //15 + val irq = Bool() //14 + val wrap = Bool() //13 + val reserved1 = UInt(4.W) //12 11 10 9 + val cf = Bool() //8 + val m = Bool() //7 + val or = Bool() //6 + val is = Bool() //5 + val dn = Bool() //4 + val tl = Bool() //3 + val sf = Bool() //2 + val crc = Bool() //1 + val lc = Bool() //0 +} + +trait MacWishboneMasterIO{ this: Bundle => + val m_wb_adr_o = Output(UInt(32.W)) + val m_wb_sel_o = Output(UInt(4.W)) + val m_wb_we_o = Output(Bool()) + val m_wb_dat_i = Input(UInt(32.W)) + val m_wb_dat_o = Output(UInt(32.W)) + val m_wb_cyc_o = Output(Bool()) + val m_wb_stb_o = Output(Bool()) + val m_wb_ack_i = Input(Bool()) + val m_wb_err_i = Input(Bool()) + val m_wb_cti_o = Output(UInt(3.W)) + val m_wb_bte_o = Output(UInt(2.W)) +} + + +trait MacWishboneSlaveIO{ this: Bundle => + val WB_DAT_I = Input(UInt(32.W)) // WISHBONE data input + val WB_DAT_O = Output(UInt(32.W)) // WISHBONE data output + + val WB_ADR_I = Input(UInt(12.W)) // WISHBONE address input + val WB_WE_I = Input(Bool()) // WISHBONE write enable input + + val WB_SEL_I = Input(UInt(4.W)) // WISHBONE byte select input + val WB_CYC_I = Input(Bool()) // WISHBONE cycle input + val WB_STB_I = Input(Bool()) // WISHBONE strobe input + + val WB_ACK_O = Output(Bool()) // WISHBONE acknowledge output + val WB_ERR_O = Output(Bool()) // WISHBONE error output +} + +trait MDIO { this: Bundle => + val mdi = Input( Bool()) // MII Management Data In + val mdc = Output(Bool()) // MII Management Data Clock + val mdo = Output(Bool()) // MII Management Data Output + val mdoEn = Output(Bool()) // MII Management Data Output Enable +} + diff --git a/src/main/scala/mac/MacTilelink.scala b/src/main/scala/mac/MacTilelink.scala index 59b2d13..b75d532 100644 --- a/src/main/scala/mac/MacTilelink.scala +++ b/src/main/scala/mac/MacTilelink.scala @@ -7,38 +7,7 @@ import freechips.rocketchip.tilelink._ import freechips.rocketchip.diplomacy._ -class TxBuffDesc extends Bundle{ - val len = UInt(16.W) //[31.16] - val rd = Bool() //[15] - val irq = Bool() //14 - val wr = Bool() //13 - val pad = Bool() //12 - val crc = Bool() //11 - val reserved1 = UInt(2.W) //10,9 - val ur = Bool() //8 - val rtry = UInt(4.W) //7 6 5 4 - val rl = Bool() //3 - val lc = Bool() //2 - val df = Bool() //1 - val cs = Bool() //0 -} -class RxBuffDesc extends Bundle{ - val len = UInt(16.W) //[31.16] - val e = Bool() //15 - val irq = Bool() //14 - val wrap = Bool() //13 - val reserved1 = UInt(4.W) //12 11 10 9 - val cf = Bool() //8 - val m = Bool() //7 - val or = Bool() //6 - val is = Bool() //5 - val dn = Bool() //4 - val tl = Bool() //3 - val sf = Bool() //2 - val crc = Bool() //1 - val lc = Bool() //0 -} @@ -55,20 +24,6 @@ abstract class MacTileLinkBase() extends Module{ class MacTileLinkIO extends Bundle{ - // WISHBONE master - val m_wb_adr_o = Output(UInt(30.W)) - val m_wb_sel_o = Output(UInt(4.W)) - val m_wb_we_o = Output(Bool()) - val m_wb_dat_o = Output(UInt(32.W)) - val m_wb_cyc_o = Output(Bool()) - val m_wb_stb_o = Output(Bool()) - val m_wb_dat_i = Input(UInt(32.W)) - val m_wb_ack_i = Input(Bool()) - val m_wb_err_i = Input(Bool()) - - val m_wb_cti_o = Output(UInt(3.W)) // Cycle Type Identifier - val m_wb_bte_o = Output(UInt(2.W)) // Burst Type Extension - // Rx Status signals val InvalidSymbol = Input(Bool()) // Invalid symbol was received during reception in 100 Mbps mode val LatchedCrcError = Input(Bool()) // CRC error @@ -127,12 +82,14 @@ abstract class MacTileLinkBase() extends Module{ val RxB_IRQ = Output(Bool()) val RxE_IRQ = Output(Bool()) val Busy_IRQ = Output(Bool()) + + } def isTileLink = false - val io = IO(new MacTileLinkIO with MacWishboneSlaveIO) + val io = IO(new MacTileLinkIO with MacWishboneSlaveIO with MacWishboneMasterIO) // if( !isTileLink ) {IO(new MacTileLinkIO with MacWishboneSlaveIO)} else {IO(new MacTileLinkIO with MacTileLinkSlaveIO)} @@ -299,7 +256,7 @@ abstract class MacTileLinkBase() extends Module{ val MasterWbTX = RegInit(false.B) val MasterWbRX = RegInit(false.B) - val m_wb_adr_o = RegInit(0.U(30.W)); io.m_wb_adr_o := m_wb_adr_o + val m_wb_adr_o = RegInit(0.U(30.W)); io.m_wb_adr_o := Cat(m_wb_adr_o, 0.U(2.W)) val m_wb_cyc_o = RegInit(false.B); io.m_wb_cyc_o := m_wb_cyc_o val m_wb_sel_o = RegInit(0.U(4.W)); io.m_wb_sel_o := m_wb_sel_o val m_wb_we_o = RegInit(false.B); io.m_wb_we_o := m_wb_we_o