fifo空间剩余

src/main/scala/backBoard/ebus/TL2CDR.scala

@@ -74,6 +74,9 @@ abstract class TL2CDRImplBase(outer: TL2CDR)(implicit p: Parameters) extends Laz
   val isTLWriteSoftReset = for( i <- 0 until 4 ) yield { Wire(Bool()) }
   val isTLReadStatus     = Wire( Bool() )
 
+  val txLeft = for( i <- 0 until 2 ) yield { RegInit(0.U(5.W)) }
+  val rxLeft = for( i <- 0 until 2 ) yield { RegInit(0.U(5.W)) }
+
 }
 
 
@@ -145,6 +148,17 @@ trait TL2CDRImplTx{ this: TL2CDRImplBase =>
 
     txFifo(i).io.enq.bits  := bus.a.bits.data
     txFifo(i).io.enq.valid := isTLWriteTxFifo(i) & txLen(i) =/= 0.U
+
+    when( isTLWriteSoftReset(0+i) ){
+      txLeft(i) := 0.U
+    } .elsewhen( txFifo(i).io.enq.fire & txFifo(i).io.deq.fire ){
+      txLeft(i) := txLeft(i)
+    } .elsewhen( txFifo(i).io.enq.fire ){
+      txLeft(i) := txLeft(i) + 1.U
+    } .elsewhen( txFifo(i).io.deq.fire ){
+      txLeft(i) := txLeft(i) - 1.U
+    }
+
   }
 
 
@@ -208,6 +222,16 @@ trait TL2CDRImplRx{ this: TL2CDRImplBase =>
       isRxError(i) := true.B
       printf(s"Warning, RxFifo$i Overflow!\n")
     }
+
+    when( isTLWriteSoftReset(2+i) ){
+      rxLeft(i) := 0.U
+    } .elsewhen( rxFifo(i).io.enq.fire & rxFifo(i).io.deq.fire ){
+      rxLeft(i) := rxLeft(i)
+    } .elsewhen( rxFifo(i).io.enq.fire ){
+      rxLeft(i) := rxLeft(i) + 1.U
+    } .elsewhen( rxFifo(i).io.deq.fire ){
+      rxLeft(i) := rxLeft(i) - 1.U
+    }
   }
 
 
@@ -403,7 +427,7 @@ with TL2CDRImplLimitTimmer
   
 
   when( isTLReadStatus ){
-    rdata := Cat( isRxValid(1), isRxValid(0), isRxError(1), isRxError(0), isTxBusy(1), isTxBusy(0), isTxFull(1), isTxFull(0) )
+    rdata := Cat( txLeft(1), txLeft(0), rxLeft(1), rxLeft(0), isRxValid(1), isRxValid(0), isRxError(1), isRxError(0), isTxBusy(1), isTxBusy(0), isTxFull(1), isTxFull(0) )
   } .elsewhen(isTLReadRxLen(0)       ){
     rdata := rxLen(0)
   } .elsewhen(isTLReadRxLen(1)       ){