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remove tx toobig

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This commit is contained in:
RuigeLee
2023-10-25 15:34:43 +08:00
parent 811c540b6b
commit 6e25f934b2
5 changed files with 14 additions and 56 deletions
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15
src/main/scala/Switch/mac/MAC.scala
View File

@@ -144,12 +144,10 @@ val MRxDV_Lb = Wire(Bool())
val MRxErr_Lb = Wire(Bool())
val MRxD_Lb = Wire(UInt(4.W))
val Transmitting = Wire(Bool())
val r_HugEn = Wire(Bool())
val r_DlyCrcEn = Wire(Bool())
val r_MaxFL = Wire(UInt(16.W))
val r_MinFL = Wire(UInt(16.W))
val DribbleNibble = Wire(Bool())
val ReceivedPacketTooBig = Wire(Bool())
val r_MAC = Wire(UInt(48.W))
val LoadRxStatus = Wire(Bool())
val r_HASH0 = Wire(UInt(32.W))
@@ -203,12 +201,10 @@ dontTouch(MRxDV_Lb )
dontTouch(MRxErr_Lb )
dontTouch(MRxD_Lb )
dontTouch(Transmitting )
dontTouch(r_HugEn )
dontTouch(r_DlyCrcEn )
dontTouch(r_MaxFL )
dontTouch(r_MinFL )
dontTouch(DribbleNibble )
dontTouch(ReceivedPacketTooBig )
dontTouch(r_MAC )
dontTouch(LoadRxStatus )
dontTouch(r_HASH0 )
@@ -283,7 +279,6 @@ io.cfg.RxClk := io.mii.mrx_clk_pad_i
io.cfg.SetPauseTimer := SetPauseTimer
r_Pad := io.cfg.r_Pad
r_HugEn := io.cfg.r_HugEn
r_CrcEn := io.cfg.r_CrcEn
r_DlyCrcEn := io.cfg.r_DlyCrcEn
r_FullD := io.cfg.r_FullD
@@ -440,7 +435,6 @@ txethmac.io.Collision := Collision
txethmac.io.Pad := PadOut
txethmac.io.CrcEn := CrcEnOut
txethmac.io.FullD := r_FullD
txethmac.io.HugEn := r_HugEn
txethmac.io.DlyCrcEn := r_DlyCrcEn
txethmac.io.MinFL := r_MinFL
txethmac.io.MaxFL := r_MaxFL
@@ -473,7 +467,6 @@ StateData := txethmac.io.StateData
val RxByteCnt = Wire(UInt(16.W))
val RxByteCntEq0 = Wire(Bool())
val RxByteCntGreat2 = Wire(Bool())
val RxByteCntMaxFrame = Wire(Bool())
val RxCrcError = Wire(Bool())
val RxStateIdle = Wire(Bool())
val RxStatePreamble = Wire(Bool())
@@ -485,7 +478,6 @@ val AddressMiss = Wire(Bool())
dontTouch(RxByteCnt )
dontTouch(RxByteCntEq0 )
dontTouch(RxByteCntGreat2 )
dontTouch(RxByteCntMaxFrame)
dontTouch(RxCrcError )
dontTouch(RxStateIdle )
dontTouch(RxStatePreamble )
@@ -498,7 +490,6 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
rxethmac.io.MRxDV := MRxDV_Lb
rxethmac.io.MRxD := MRxD_Lb
rxethmac.io.Transmitting := Transmitting
rxethmac.io.HugEn := r_HugEn
rxethmac.io.DlyCrcEn := r_DlyCrcEn
rxethmac.io.MaxFL := r_MaxFL
rxethmac.io.r_IFG := r_IFG
@@ -515,7 +506,6 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
RxByteCnt := rxethmac.io.ByteCnt
RxByteCntEq0 := rxethmac.io.ByteCntEq0
RxByteCntGreat2 := rxethmac.io.ByteCntGreat2
RxByteCntMaxFrame := rxethmac.io.ByteCntMaxFrame
RxCrcError := rxethmac.io.CrcError
RxStateIdle := rxethmac.io.StateIdle
RxStatePreamble := rxethmac.io.StatePreamble
@@ -609,13 +599,11 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
macstatus.io.RxByteCnt := RxByteCnt
macstatus.io.RxByteCntEq0 := RxByteCntEq0
macstatus.io.RxByteCntGreat2 := RxByteCntGreat2
macstatus.io.RxByteCntMaxFrame := RxByteCntMaxFrame
macstatus.io.MRxD := MRxD_Lb
macstatus.io.Collision := io.mii.mcoll_pad_i
macstatus.io.CollValid := r_CollValid
macstatus.io.r_MinFL := r_MinFL
macstatus.io.r_MaxFL := r_MaxFL
macstatus.io.r_HugEn := r_HugEn
macstatus.io.StartTxDone := StartTxDone
macstatus.io.StartTxAbort := StartTxAbort
macstatus.io.MTxClk := io.mii.mtx_clk_pad_i
@@ -636,7 +624,6 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
LatchedCrcError := macstatus.io.LatchedCrcError
RxLateCollision := macstatus.io.RxLateCollision
DribbleNibble := macstatus.io.DribbleNibble
ReceivedPacketTooBig := macstatus.io.ReceivedPacketTooBig
LoadRxStatus := macstatus.io.LoadRxStatus
RetryLimit := macstatus.io.RetryLimit
LateCollLatched := macstatus.io.LateCollLatched
@@ -760,7 +747,7 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
macTileLinkRx.io.RxLength := RxByteCnt
macTileLinkRx.io.LoadRxStatus := LoadRxStatus
macTileLinkRx.io.RxStatusIn := Cat(ReceivedPauseFrm, AddressMiss, false.B, false.B, DribbleNibble, ReceivedPacketTooBig, false.B, LatchedCrcError, RxLateCollision)
macTileLinkRx.io.RxStatusIn := Cat(ReceivedPauseFrm, AddressMiss, false.B, false.B, DribbleNibble, false.B, false.B, LatchedCrcError, RxLateCollision)
wishbone.io.rxEnq <> io.rxEnq

17
src/main/scala/Switch/mac/MacRx.scala
View File

@@ -10,7 +10,6 @@ class MacRxIO extends Bundle{
val MRxDV = Input(Bool())
val MRxD = Input(UInt(4.W))
val Transmitting = Input(Bool())
val HugEn = Input(Bool())
val DlyCrcEn = Input(Bool())
val MaxFL = Input(UInt(16.W))
val r_IFG = Input(Bool())
@@ -27,7 +26,6 @@ class MacRxIO extends Bundle{
val ByteCnt = Output(UInt(16.W))
val ByteCntEq0 = Output(Bool())
val ByteCntGreat2 = Output(Bool())
val ByteCntMaxFrame = Output(Bool())
val CrcError = Output(Bool())
val StateIdle = Output(Bool())
val StatePreamble = Output(Bool())
@@ -86,9 +84,9 @@ trait MacRxFSM { this: MacRxBase =>
val StartPreamble = io.MRxDV & ~MRxDEq5 & (StateIdle & ~io.Transmitting)
val StartSFD = io.MRxDV & MRxDEq5 & (StateIdle & ~io.Transmitting | StatePreamble)
val StartData0 = io.MRxDV & (StateSFD & MRxDEqD & IFGCounterEq24 | StateData1)
val StartData1 = io.MRxDV & StateData0 & (~io.ByteCntMaxFrame)
val StartData1 = io.MRxDV & StateData0
val StartDrop = io.MRxDV & (
(StateIdle & io.Transmitting) | (StateSFD & ~IFGCounterEq24 & MRxDEqD ) | ( StateData0 & io.ByteCntMaxFrame)
(StateIdle & io.Transmitting) | (StateSFD & ~IFGCounterEq24 & MRxDEqD )
)
@@ -139,7 +137,7 @@ trait MacRxCounter { this: MacRxBase =>
val ByteCntMax = ByteCnt === "hffff".U
val ResetByteCounter = io.MRxDV & (io.StateSFD & MRxDEqD | io.StateData.extract(0) & io.ByteCntMaxFrame)
val ResetByteCounter = io.MRxDV & (io.StateSFD & MRxDEqD)
val IncrementByteCounter =
~ResetByteCounter & io.MRxDV & (
@@ -176,9 +174,6 @@ trait MacRxCounter { this: MacRxBase =>
io.ByteCntGreat2 := ByteCnt > 2.U
ByteCntSmall7 := ByteCnt < 7.U
io.ByteCntMaxFrame := (ByteCnt === io.MaxFL) & ~io.HugEn;
val ResetIFGCounter = io.StateSFD & io.MRxDV & MRxDEqD | StateDrop;
val IncrementIFGCounter = ~ResetIFGCounter & (StateDrop | io.StateIdle | io.StatePreamble | io.StateSFD) & ~IFGCounterEq24;
@@ -236,7 +231,7 @@ trait MacRxFAddrCheck { this: MacRxBase =>
trait MacRxCRC { this: MacRxBase =>
val Data_Crc = Cat(io.MRxD.extract(0),io.MRxD.extract(1),io.MRxD.extract(2),io.MRxD.extract(3))
val Enable_Crc = io.MRxDV & (io.StateData.orR & ~io.ByteCntMaxFrame)
val Enable_Crc = io.MRxDV & (io.StateData.orR)
val Initialize_Crc = io.StateSFD | (io.DlyCrcEn & DlyCrcCnt > 0.U & DlyCrcCnt < 9.U)
when( Initialize_Crc ){
@@ -312,8 +307,8 @@ class MacRx extends MacRxBase with MacRxFSM with MacRxCounter with MacRxFAddrChe
io.RxStartFrm := ShiftRegister(GenerateRxStartFrm, 2, false.B, true.B)
val GenerateRxEndFrm = StateData0 & ((~io.MRxDV & io.ByteCntGreat2) | io.ByteCntMaxFrame)
val DribbleRxEndFrm = StateData1 & ~io.MRxDV & io.ByteCntGreat2
val GenerateRxEndFrm = StateData0 & (~io.MRxDV & io.ByteCntGreat2)
val DribbleRxEndFrm = StateData1 & ~io.MRxDV & io.ByteCntGreat2
val RxEndFrm_d = RegNext(GenerateRxEndFrm, false.B)
io.RxEndFrm := RegNext(RxEndFrm_d | DribbleRxEndFrm, false.B)

17
src/main/scala/Switch/mac/MacStatus.scala
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@@ -18,13 +18,11 @@ class MacStatusIO extends Bundle{
val RxByteCnt = Input(UInt(16.W))
val RxByteCntEq0 = Input(Bool())
val RxByteCntGreat2 = Input(Bool())
val RxByteCntMaxFrame = Input(Bool())
val MRxD = Input(UInt(4.W))
val Collision = Input(Bool())
val CollValid = Input(UInt(6.W))
val r_MinFL = Input(UInt(16.W))
val r_MaxFL = Input(UInt(16.W))
val r_HugEn = Input(Bool())
val StartTxDone = Input(Bool())
val StartTxAbort = Input(Bool())
val MTxClk = Input(Bool())
@@ -45,7 +43,6 @@ class MacStatusIO extends Bundle{
val LatchedCrcError = Output(Bool())
val RxLateCollision = Output(Bool())
val DribbleNibble = Output(Bool())
val ReceivedPacketTooBig = Output(Bool())
val LoadRxStatus = Output(Bool())
val RetryLimit = Output(Bool())
val LateCollLatched = Output(Bool())
@@ -73,9 +70,7 @@ class MacStatus extends RawModule{
// Time to take a sample
val TakeSample =
(io.RxStateData.orR & ~io.MRxDV) |
(io.RxStateData.extract(0) & io.MRxDV & io.RxByteCntMaxFrame)
(io.RxStateData.orR & ~io.MRxDV)
val LoadRxStatus = RegNext(TakeSample, false.B); io.LoadRxStatus := LoadRxStatus // LoadRxStatus
val ReceiveEnd = RegNext(LoadRxStatus, false.B); io.ReceiveEnd := ReceiveEnd // ReceiveEnd
@@ -110,16 +105,6 @@ class MacStatus extends RawModule{
DribbleNibble := true.B
}
val ReceivedPacketTooBig = RegInit(false.B); io.ReceivedPacketTooBig := ReceivedPacketTooBig
when(LoadRxStatus){
ReceivedPacketTooBig := false.B
} .elsewhen(TakeSample){
ReceivedPacketTooBig := ~io.r_HugEn & io.RxByteCnt > io.r_MaxFL
}
}

19
src/main/scala/Switch/mac/MacTx.scala
View File

@@ -14,7 +14,6 @@ class MacTxIO extends Bundle{
val Pad = Input(Bool()) // Pad enable (from register)
val CrcEn = Input(Bool()) // Crc enable (from register)
val FullD = Input(Bool()) // Full duplex (from register)
val HugEn = Input(Bool()) // Huge packets enable (from register)
val DlyCrcEn = Input(Bool()) // Delayed Crc enabled (from register)
val MinFL = Input(UInt(16.W)) // Minimum frame length (from register)
val MaxFL = Input(UInt(16.W)) // Maximum frame length (from register)
@@ -60,16 +59,12 @@ abstract class MacTxBase extends Module with RequireAsyncReset{
val StateSFD = Wire(Bool())
val TooBig = Wire(Bool())
val CrcError = Wire(Bool())
val NibbleMinFl = Wire(Bool())
val ExcessiveDefer = Wire(Bool())
val MaxFrame = Wire(Bool())
val StateIPG = RegInit(false.B)
val StateIdle = RegInit(false.B)
val StatePreamble = RegInit(false.B); io.StatePreamble := StatePreamble
@@ -103,7 +98,7 @@ trait MacTxFSM { this: MacTxBase =>
StartPreamble := StateIdle & io.TxStartFrm & ~io.CarrierSense
StartData(0) := ~io.Collision & (StatePreamble & NibCntEq15 | StateData(1) & ~io.TxEndFrm)
StartData(1) := ~io.Collision & StateData(0) & ~MaxFrame
StartData(1) := ~io.Collision & StateData(0)
val StartPAD = ~io.Collision & StateData(1) & io.TxEndFrm & io.Pad & ~NibbleMinFl
@@ -117,8 +112,7 @@ trait MacTxFSM { this: MacTxBase =>
(StateIPG & ~Rule1 & io.CarrierSense & NibCnt(6,0) <= io.IPGR1 & NibCnt(6,0) =/= io.IPGR2) |
(StateIdle & io.CarrierSense) |
(StateJam & NibCntEq7) |
io.StartTxDone |
TooBig
io.StartTxDone
io.DeferIndication := StateIdle & io.CarrierSense
@@ -219,8 +213,6 @@ trait MacTxCounter { this: MacTxBase =>
} .elsewhen(IncrementByteCnt){
ByteCnt := ByteCnt + 1.U
}
MaxFrame := (ByteCnt === io.MaxFL) & ~io.HugEn;
when((StateData(1) & DlyCrcCnt === 4.U) | StartJam | PacketFinished_q){
DlyCrcCnt := 0.U
@@ -300,7 +292,7 @@ class MacTx extends MacTxBase with MacTxFSM with MacTxCounter with MacTxCRC {
val TxAbort = RegInit(false.B); io.TxAbort := TxAbort
val MTxEn = RegNext(StatePreamble | (StateData(0) | StateData(1)) | StatePAD | StateFCS | StateJam, false.B); io.MTxEn := MTxEn
val MTxErr = RegNext( TooBig, false.B); io.MTxErr := MTxErr// Transmit error
io.MTxErr := false.B
val WillTransmit = RegNext(StartPreamble | StatePreamble | (StateData(0) | StateData(1)) | StatePAD | StateFCS | StateJam, false.B); io.WillTransmit := WillTransmit// WillTransmit
@@ -309,11 +301,10 @@ class MacTx extends MacTxBase with MacTxFSM with MacTxCounter with MacTxCRC {
io.ResetCollision := ~(StatePreamble | (StateData(0) | StateData(1)) | StatePAD | StateFCS)
val ExcessiveDeferOccured = io.TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured
io.StartTxDone := ~io.Collision & (StateFCS & NibCntEq7 | StateData(1) & io.TxEndFrm & (~io.Pad | io.Pad & NibbleMinFl) & ~io.CrcEn)
TooBig := ~io.Collision & MaxFrame & (StateData(0) | StateFCS);
io.LateCollision := StartJam & ~ColWindow
io.MaxCollisionOccured := StartJam & ColWindow;
StateSFD := StatePreamble & NibCntEq15;
io.StartTxAbort := TooBig | ExcessiveDeferOccured | io.LateCollision | io.MaxCollisionOccured
io.StartTxAbort := ExcessiveDeferOccured | io.LateCollision | io.MaxCollisionOccured
when(~io.TxStartFrm){
StopExcessiveDeferOccured := false.B
@@ -373,7 +364,7 @@ class MacTx extends MacTxBase with MacTxFSM with MacTxCounter with MacTxCRC {
)
}
val PacketFinished_d = io.StartTxDone | TooBig | io.LateCollision | io.MaxCollisionOccured | ExcessiveDeferOccured;
val PacketFinished_d = io.StartTxDone | io.LateCollision | io.MaxCollisionOccured | ExcessiveDeferOccured;
val PacketFinished = RegNext(PacketFinished_d, false.B)
when(true.B){
PacketFinished_q := PacketFinished