锁定后，每16个cycle ，或许有bug

src/main/scala/backBoard/ebus/CDRIn.scala

@@ -67,6 +67,7 @@ trait CDRInOverSample{ this: CDRInBase =>
 trait CDRInMultiSample{ this: CDRInBase =>
   
   val clkNum: Int = 16
+  require( clkNum == 16 )
 
 
   //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
@@ -111,7 +112,8 @@ trait CDRInMultiSample{ this: CDRInBase =>
     }
 
   val clearCnt = Reg(UInt(4.W))
-  val arbLock = Reg(UInt( clkNum.W ))
+  val checkCnt = Reg(UInt(4.W))
+  val arbLock = Reg(UInt( (log2Ceil(clkNum)+1).W ))
   val isLock = RegInit(false.B)
 
   when( sampleReg.reduce(_|_) === false.B ){
@@ -122,13 +124,36 @@ trait CDRInMultiSample{ this: CDRInBase =>
     clearCnt := 0.U
   }
 
+  when( sampleReg.reduce(_|_) === false.B ){
+    checkCnt := 0.U
+  } .otherwise{
+    checkCnt := checkCnt + 1.U
+  }
 
   //优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的
+
+    for( i <- 0 + 4 until clkNum + 4 ){
+      val j = clkNum + 4 - i -1
+      val diff = Wire(UInt( (log2Ceil(clkNum)).W ))
+      diff := arbLock - j.U
+      when( flitReg(j) ^ flitReg(j+1) ){
+        when( ~isLock ){
+          arbLock := j.U
+          isLock := true.B
+        } .elsewhen( checkCnt.andR ){ //锁定之后，只允许每16cycle移动一相位
+          when( diff > 8.U ){
+            arbLock := arbLock + 1.U
+          } .elsewhen( diff < 8.U ){
+            arbLock := arbLock - 1.U
+          }
+        }
+      }
+    }
+    
   when( ~isLock ){    
     for( i <- 0 until clkNum ){
       val j = clkNum - i -1
       when( flitReg(j) ^ flitReg(j+1) ){
-        arbLock := "b1".U(clkNum.W) << j
         isLock := true.B
       }
     }
@@ -139,8 +164,8 @@ trait CDRInMultiSample{ this: CDRInBase =>
 
   val asyncSerDat = 
     Mux1H(
-      (for { i <- 0 until clkNum } yield {
+      (for { i <- 4 until clkNum+4 } yield {
-        (arbLock === (1.U << i)) -> flitReg(i+(clkNum/2))
+        (arbLock === i.U) -> flitReg(i+(clkNum/2))
       })
     )