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This commit is contained in:
RuigeLee
2023-07-19 11:30:26 +08:00
parent e3e1f6b6cb
commit 6cb9d0982e
24 changed files with 0 additions and 3946 deletions
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5
tb/sw/.gitignore vendored
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*.elf
*.o
*.img
*.bin

40
tb/sw/axi_gpio/gpio.c
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#include <stdint.h>
#include "gpio.h"
#ifndef GPIO_BASE
#error GPIO Base address not define!!!
#endif
// for 8 bit gpio
volatile uint32_t *gpio_dat_reg = (uint32_t*)( GPIO_BASE + GPIO_DATA );
volatile uint32_t *gpio_tri_reg = (uint32_t*)( GPIO_BASE + GPIO_TRI );
uint8_t gpio_read()
{
*gpio_tri_reg = 0xff;
return (uint8_t)(*gpio_dat_reg);
}
uint32_t gpio_write( uint32_t data )
{
*gpio_tri_reg = 0x00;
(*gpio_dat_reg) = data;
return 0;
}

24
tb/sw/axi_gpio/gpio.h
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#ifndef _GPIO_H_
#define _GPIO_H_
#include <stdint.h>
#define GPIO_BASE 0x20000000U
#define GPIO_DATA 0x0000
#define GPIO_TRI 0x0004
#define GPIO2_DATA 0x0008
#define GPIO2_TRI 0x000C
#define GIER 0x011C
#define IP_IER 0x0128
#define IP_ISR 0x0120
extern uint8_t gpio_read();
extern uint32_t gpio_write( uint32_t data );
void gpio_test();
#endif

232
tb/sw/axi_timer/timer.c
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/*
* @Author: Ruige Lee
* @Date: 2020-10-12 14:27:54
* @Last Modified by: Ruige Lee
* @Last Modified time: 2020-10-12 17:16:04
*/
#include <stdint.h>
#include "timer.h"
#ifndef TIMER_BASE
#error Timer Base address not define!!!
#endif
volatile uint32_t *timer_tcsr0_reg = (uint32_t*)( TIMER_BASE + TIMER_TCSR0 );
volatile uint32_t *timer_tlr0_reg = (uint32_t*)( TIMER_BASE + TIMER_TLR0 );
volatile uint32_t *timer_tcr0_reg = (uint32_t*)( TIMER_BASE + TIMER_TCR0 );
volatile uint32_t *timer_tcsr1_reg = (uint32_t*)( TIMER_BASE + TIMER_TCSR1 );
volatile uint32_t *timer_tlr1_reg = (uint32_t*)( TIMER_BASE + TIMER_TLR1 );
volatile uint32_t *timer_tcr1_reg = (uint32_t*)( TIMER_BASE + TIMER_TCR1 );
int32_t timerIsINT(uint8_t timerNo)
{
if ( ( ( (*timer_tcsr0_reg) & 0x00000100 ) && ( timerNo == 0 ) )
||
( ( (*timer_tcsr1_reg) & 0x00000100 ) && ( timerNo == 1 ) )
)
{
return 1;
}
else
{
return 0;
}
}
int32_t timerClearINT(uint8_t timerNo)
{
if ( timerNo == 0 )
{
*timer_tcsr0_reg = (*timer_tcsr0_reg) | 0x00000100;
}
else
{
*timer_tcsr1_reg = (*timer_tcsr1_reg) | 0x00000100;
}
return 0;
}
int32_t timerEnableRun(uint8_t timerNo)
{
if ( timerNo == 0 )
{
*timer_tcsr0_reg = (*timer_tcsr0_reg) | 0x00000080;
}
else
{
*timer_tcsr1_reg = (*timer_tcsr1_reg) | 0x00000080;
}
return 0;
}
int32_t timerDisableRun(uint8_t timerNo)
{
if ( timerNo == 0 )
{
*timer_tcsr0_reg = (*timer_tcsr0_reg) & (~0x00000080);
}
else
{
*timer_tcsr1_reg = (*timer_tcsr1_reg) & (~0x00000080);
}
return 0;
}
int32_t timerEnableINT(uint8_t timerNo)
{
if ( timerNo == 0 )
{
*timer_tcsr0_reg = (*timer_tcsr0_reg) & (~0x00000020);
*timer_tcsr0_reg = (*timer_tcsr0_reg) | 0x00000040;
}
else
{
*timer_tcsr1_reg = (*timer_tcsr1_reg) & (~0x00000020);
*timer_tcsr1_reg = (*timer_tcsr1_reg) | 0x00000040;
}
return 0;
}
int32_t timerDisableINT(uint8_t timerNo)
{
if ( timerNo == 0 )
{
*timer_tcsr0_reg = (*timer_tcsr0_reg) & (~0x00000040);
}
else
{
*timer_tcsr1_reg = (*timer_tcsr1_reg) & (~0x00000040);
}
return 0;
}
int32_t timerLoad(uint8_t timerNo, uint32_t count)
{
if ( timerNo == 0 )
{
*timer_tlr0_reg = count;
*timer_tcsr0_reg = (*timer_tcsr0_reg) | 0x00000020;
}
else
{
*timer_tlr1_reg = count;
*timer_tcsr1_reg = (*timer_tcsr1_reg) | 0x00000020;
}
return 0;
}
int32_t timerAutoReloadEnable(uint8_t timerNo)
{
if ( timerNo == 0 )
{
*timer_tcsr0_reg = (*timer_tcsr0_reg) | 0x00000010;
}
else
{
*timer_tcsr1_reg = (*timer_tcsr1_reg) | 0x00000010;
}
return 0;
}
int32_t timerAutoReloadDisable(uint8_t timerNo)
{
if ( timerNo == 0 )
{
*timer_tcsr0_reg = (*timer_tcsr0_reg) & (~0x00000010);
}
else
{
*timer_tcsr1_reg = (*timer_tcsr1_reg) & (~0x00000010);
}
return 0;
}
int32_t timerUpCount(uint8_t timerNo)
{
if ( timerNo == 0 )
{
*timer_tcsr0_reg = (*timer_tcsr0_reg) & (~0x00000002);
}
else
{
*timer_tcsr1_reg = (*timer_tcsr1_reg) & (~0x00000002);
}
return 0;
}
int32_t timerDownCount(uint8_t timerNo)
{
if ( timerNo == 0 )
{
*timer_tcsr0_reg = (*timer_tcsr0_reg) | 0x00000002;
}
else
{
*timer_tcsr1_reg = (*timer_tcsr1_reg) | 0x00000002;
}
return 0;
}
int32_t timerGenerate(uint8_t timerNo)
{
if ( timerNo == 0 )
{
*timer_tcsr0_reg = (*timer_tcsr0_reg) & (~0x00000001);
}
else
{
*timer_tcsr1_reg = (*timer_tcsr1_reg) & (~0x00000001);
}
return 0;
}
int32_t timerCapture( uint8_t timerNo )
{
if ( timerNo == 0 )
{
*timer_tcsr0_reg = (*timer_tcsr0_reg) | 0x00000001;
}
else
{
*timer_tcsr1_reg = (*timer_tcsr1_reg) | 0x00000001;
}
return 0;
}
uint32_t timerCounterRead( uint8_t timerNo )
{
if ( timerNo == 0 )
{
return *timer_tcr0_reg;
}
else
{
return *timer_tcr1_reg;
}
}

50
tb/sw/axi_timer/timer.h
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#ifndef _TIMER_H_
#define _TIMER_H_
#include <stdint.h>
#define TIMER_BASE 0x20000800U
#define TIMER_TCSR0 0x00U
#define TIMER_TLR0 0x04
#define TIMER_TCR0 0x08
// #define TIMER_RSVD
#define TIMER_TCSR1 0x10U
#define TIMER_TLR1 0x14U
#define TIMER_TCR1 0x18U
extern int32_t timerIsINT( uint8_t timerNo );
extern int32_t timerClearINT( uint8_t timerNo );
extern int32_t timerEnableRun( uint8_t timerNo );
extern int32_t timerDisableRun( uint8_t timerNo );
extern int32_t timerEnableINT( uint8_t timerNo );
extern int32_t timerDisableINT( uint8_t timerNo );
extern int32_t timerLoad( uint8_t timerNo, uint32_t count );
extern int32_t timerAutoReloadEnable( uint8_t timerNo );
extern int32_t timerAutoReloadDisable( uint8_t timerNo );
extern int32_t timerUpCount( uint8_t timerNo );
extern int32_t timerDownCount( uint8_t timerNo );
extern int32_t timerGenerate( uint8_t timerNo );
extern int32_t timerCapture( uint8_t timerNo );
extern uint32_t timerCounterRead( uint8_t timerNo );
#endif

79
tb/sw/axi_uart/uart.c
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#include <stdint.h>
#include "uart.h"
#ifndef UART_BASE
#error UART Base address not define!!!
#endif
volatile uint32_t *uart_rfifo = (uint32_t*)( UART_BASE + RX_FIFO );
volatile uint32_t *uart_tfifo = (uint32_t*)( UART_BASE + TX_FIFO );
volatile uint32_t *uart_status = (uint32_t*)( UART_BASE + STAT_REG );
volatile uint32_t *uart_ctrl = (uint32_t*)( UART_BASE + CTRL_REG );
int32_t uart_init()
{
//reset rx & tx fifo, disable interrupt
(*uart_status) = 0x03;
(*uart_status) = 0x00;
return 0;
}
int32_t uart_sendByte( uint8_t data )
{
uint64_t sent = (uint64_t)data << 32;
#if(0)
//wait unitl tx fifo not full
while( ((*uart_status) & 0x08) != 0);
(*(volatile uint64_t*)(UART_BASE)) = sent;
#else
(*(volatile uint64_t*)(0x60000000)) = sent;
#endif
return 0;
}
uint8_t uart_recByte()
{
//wait unitl rx fifo has data
while( ((*uart_status) & 0x01) == 0);
return (uint8_t)(*uart_rfifo);
}
int32_t print_uart(const char *str)
{
const char *cur = &str[0];
while (*cur != '\0')
{
uart_sendByte((uint8_t)*cur);
cur++;
}
return 0;
}

26
tb/sw/axi_uart/uart.h
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#ifndef _UART_H_
#define _UART_H_
#include <stdint.h>
#define UART_BASE 0x20600000U
#define RX_FIFO 0x0000
#define TX_FIFO 0x0004
#define STAT_REG 0x0008
#define CTRL_REG 0x000c
extern int32_t uart_init();
extern int32_t uart_sendByte( uint8_t data );
extern uint8_t uart_recByte();
extern int32_t print_uart(const char *str);
#endif

39
tb/sw/linker.lds
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ENTRY(_prog_start)
SECTIONS
{
RAM_BASE = 0x80000000;
. = RAM_BASE;
.text.init : { *(.text.init) }
.text : ALIGN(0x100) {
_TEXT_START_ = .;
*(.text)
_TEXT_END_ = .;
}
.data : ALIGN(0x100) {
_DATA_START_ = .;
*(.data)
_DATA_END_ = .;
}
PROVIDE(_data = ADDR(.data));
PROVIDE(_data_lma = LOADADDR(.data));
PROVIDE(_edata = .);
.bss : ALIGN(0x100) {
_BSS_START_ = .;
*(.bss)
_BSS_END_ = .;
}
.rodata : ALIGN(0x100) {
_RODATA_START_ = .;
*(.rodata)
*(.rodata*)
_RODATA_END_ = .;
}
}

38
tb/sw/src/main.c
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#include <stdint.h>
#include "uart.h"
#include "gpio.h"
#include "timer.h"
int main()
{
// uart_init();
print_uart("Hello World, RocketChip is now Waking Up!\r\n");
// gpio_write( 0xfffffffa );
uint8_t i = 0;
uint32_t data = 0;
volatile uint32_t* reg = (uint32_t*)(0x80002000);
for ( i = 0; i < 255; i++ )
{
*(reg+i) = data;
data ++;
}
while(1)
{
;
}
return 0;
}
void handle_trap(void)
{
}

156
tb/sw/src/startup.S
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.section .text.init
.globl _prog_start
_prog_start:
li x1, 0
li x2, 0
li x3, 0
li x4, 0
li x5, 0
li x6, 0
li x7, 0
li x8, 0
li x9, 0
li x10,0
li x11,0
li x12,0
li x13,0
li x14,0
li x15,0
li x16,0
li x17,0
li x18,0
li x19,0
li x20,0
li x21,0
li x22,0
li x23,0
li x24,0
li x25,0
li x26,0
li x27,0
li x28,0
li x29,0
li x30,0
li x31,0
li t0, 0xffff
csrc mie, t0
li t0, 0xa
csrc mstatus, t0
# csrwi satp,0
# li t0,-1
# csrw pmpaddr0,t0
# li t0,31
# csrw pmpcfg0,t0
# csrwi medeleg,0
# csrwi mideleg,0
# li t0, 1
# slli t0, t0, 31
# csrw mtvec,t0
# csrwi mie, 0
# csrwi mstatus,0
li sp, 0x80001000
# li t1, 0x80000200
# li t2, -1
# sd t2, 0(t1)
# li t1,0x80000000
# jr t1
la t0, trap_entry
csrw mtvec, t0
call main
li gp, 1;
ecall
trap_entry:
addi sp, sp, -136
sw x1, 1* 4(sp)
sw x2, 2* 4(sp)
sw x3, 3* 4(sp)
sw x4, 4* 4(sp)
sw x5, 5* 4(sp)
sw x6, 6* 4(sp)
sw x7, 7* 4(sp)
sw x8, 8* 4(sp)
sw x9, 9* 4(sp)
sw x10, 10*4(sp)
sw x11, 11*4(sp)
sw x12, 12*4(sp)
sw x13, 13*4(sp)
sw x14, 14*4(sp)
sw x15, 15*4(sp)
sw x16, 16*4(sp)
sw x17, 17*4(sp)
sw x18, 18*4(sp)
sw x19, 19*4(sp)
sw x20, 20*4(sp)
sw x21, 21*4(sp)
sw x22, 22*4(sp)
sw x23, 23*4(sp)
sw x24, 24*4(sp)
sw x25, 25*4(sp)
sw x26, 26*4(sp)
sw x27, 27*4(sp)
sw x28, 28*4(sp)
sw x29, 29*4(sp)
sw x30, 30*4(sp)
sw x31, 31*4(sp)
csrr a0, mcause
csrr a1, mepc
mv a2, sp
jal handle_trap
# csrw mepc, a0
# li t0, MSTATUS_MPP
# csrs mstatus, t0
lw x1, 1 *4(sp)
lw x2, 2 *4(sp)
lw x3, 3 *4(sp)
lw x4, 4 *4(sp)
lw x5, 5 *4(sp)
lw x6, 6 *4(sp)
lw x7, 7 *4(sp)
lw x8, 8 *4(sp)
lw x9, 9 *4(sp)
lw x10, 10*4(sp)
lw x11, 11*4(sp)
lw x12, 12*4(sp)
lw x13, 13*4(sp)
lw x14, 14*4(sp)
lw x15, 15*4(sp)
lw x16, 16*4(sp)
lw x17, 17*4(sp)
lw x18, 18*4(sp)
lw x19, 19*4(sp)
lw x20, 20*4(sp)
lw x21, 21*4(sp)
lw x22, 22*4(sp)
lw x23, 23*4(sp)
lw x24, 24*4(sp)
lw x25, 25*4(sp)
lw x26, 26*4(sp)
lw x27, 27*4(sp)
lw x28, 28*4(sp)
lw x29, 29*4(sp)
lw x30, 30*4(sp)
lw x31, 31*4(sp)
addi sp, sp, 136
mret