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master的 req延迟一拍，使得0x20寄存器可以修改的同时发起请求

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This commit is contained in:
Ruige Lee
2025-05-27 10:30:48 +08:00
parent 65ea42d5dd
commit 6b74a9eed5
2 changed files with 4 additions and 2 deletions
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2
src/main/scala/backBoard/shin/Interface.scala
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@@ -813,7 +813,7 @@ with InterfaceSystem
io.txReq.bits.txSM := mReg.txSM
io.txReq.bits.rxSM := mReg.rxSM
// io.txReq.bits.txLength := //mReg.txLength
io.txReq.valid := isEnW & addrw === "h20".U & dataw.extract(0) === "b1".U //& mReg.txLength =/= 0.U
io.txReq.valid := RegNext(isEnW & addrw === "h20".U & dataw.extract(0) === "b1".U, false.B) //& mReg.txLength =/= 0.U